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參數(shù)資料
| 型號： | SAB-XC167CI-16F20F |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | 0.50 MM PITCH, PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 42/80頁 |
| 文件大小： | 2477K |
| 代理商： | SAB-XC167CI-16F20F |
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XC167
Derivatives
Functional Description
Data Sheet
43
V1.1, 2003-06
Preliminary
3.16
Clock Generation
The Clock Generation Unit uses a programmable on-chip PLL with multiple prescalers
to generate the clock signals for the XC167 with high flexibility. The master clock
fMC is
the reference clock signal, and is used for TwinCAN and is output to the external system.
The CPU clock
fCPU and the system clock fSYS are derived from the master clock either
directly (1:1) or via a 2:1 prescaler (
The on-chip oscillator can drive an external crystal or accepts an external clock signal.
The oscillator clock frequency can be multiplied by the on-chip PLL (by a programmable
factor) or can be divided by a programmable prescaler factor.
If the bypass mode is used (direct drive or prescaler) the PLL can deliver an independent
clock to monitor the clock signal generated by the on-chip oscillator. This PLL clock is
independent from the XTAL1 clock. When the expected oscillator clock transitions are
missing the Oscillator Watchdog (OWD) activates the PLL Unlock / OWD interrupt node
and supplies the CPU with an emergency clock, the PLL clock signal. Under these
circumstances the PLL will oscillate with its basic frequency.
The oscillator watchdog can be disabled by switching the PLL off. This reduces power
consumption, but also no interrupt request will be generated in case of a missing
oscillator clock.
Note: At the end of an external reset (EA = ‘0’) the oscillator watchdog may be disabled
via hardware by (externally) pulling the RD line low upon a reset, similar to the
standard reset configuration.
3.17
Parallel Ports
The XC167 provides up to 103 I/O lines which are organized into nine input/output ports
and one input port. All port lines are bit-addressable, and all input/output lines are
individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O
ports are true bidirectional ports which are switched to high impedance state when
configured as inputs. The output drivers of some I/O ports can be configured (pin by pin)
for push/pull operation or open-drain operation via control registers. During the internal
reset, all port pins are configured as inputs (except for pin RSTOUT).
The edge characteristics (shape) and driver characteristics (output current) of the port
drivers can be selected via registers POCONx.
The input threshold of some ports is selectable (TTL or CMOS like), where the special
CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The
input threshold may be selected individually for each byte of the respective ports.
All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as general
purpose IO lines.
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