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參數(shù)資料
| 型號： | SAB-XC167CI-16F20F |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | 0.50 MM PITCH, PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 61/80頁 |
| 文件大?。?/td> | 2477K |
| 代理商： | SAB-XC167CI-16F20F |
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XC167
Derivatives
Timing Parameters
Data Sheet
60
V1.1, 2003-06
Preliminary
5
Timing Parameters
5.1
Definition of Internal Timing
The internal operation of the XC167 is controlled by the internal master clock
fMC.
The master clock signal
fMC can be generated from the oscillator clock signal fOSC via
different mechanisms. The duration of master clock periods (TCMs) and their variation
(and also the derived external timing) depend on the used mechanism to generate
fMC.
This influence must be regarded when calculating the timings for the XC167.
Figure 15
Generation Mechanisms for the Master Clock
Note: The example for PLL operation shown in Figure 15 refers to a PLL factor of 1:4,
the example for prescaler operation refers to a divider factor of 2:1.
The used mechanism to generate the master clock is selected by register PLLCON.
CPU and EBC are clocked with the CPU clock signal
fCPU. The CPU clock can have the
same frequency as the master clock (
fCPU = fMC) or can be the master clock divided by
two:
fCPU = fMC / 2. This factor is selected by bit CPSYS in register SYSCON1.
The specification of the external timing (AC Characteristics) depends on the period of the
CPU clock, called “TCP”.
The other peripherals are supplied with the system clock signal
fSYS which has the same
frequency as the CPU clock signal
fCPU.
TCM
fMC
fOSC
fMC
fOSC
Phase Locked Loop Operation (1:N)
Direct Clock Drive (1:1)
TCM
fMC
fOSC
Prescaler Operation (N:1)
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