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參數(shù)資料
| 型號： | SAB-XC167CI-16F20F |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | 0.50 MM PITCH, PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 31/80頁 |
| 文件大?。?/td> | 2477K |
| 代理商： | SAB-XC167CI-16F20F |
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XC167
Derivatives
Functional Description
Data Sheet
33
V1.1, 2003-06
Preliminary
Figure 7
Block Diagram of GPT1
With its maximum resolution of 2 system clock cycles, the GPT2 module provides
precise event control and time measurement. It includes two timers (T5, T6) and a
capture/reload register (CAPREL). Both timers can be clocked with an input clock which
is derived from the CPU clock via a programmable prescaler or with external signals. The
count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD).
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5, and/or it may be output on pin
T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the
CAPCOM1/2 timers, and to cause a reload from the CAPREL register.
The CAPREL register may capture the contents of timer T5 based on an external signal
transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared
T3
Mo de
C ontro l
2 n : 1
f
SY S
2 n : 1
f
SY S
T2
Mo de
C ontro l
G P T1 Tim e r T2
Reloa d
C apture
2 n : 1
f
SY S
T4
Mo de
C ontro l
G P T1 Tim e r T4
Reloa d
C apture
G P T1 Tim e r T3
T3O T L
U/D
T2EU D
T2IN
T3IN
T3EU D
T4IN
T4EU D
Toggle FF
U/D
In te rru pt
R equest
(T 2 IR )
In te rru pt
R equest
(T 3 IR )
In te rru pt
R equest
(T 4 IR )
M c t04825_xc.v sd
T6 O U T
n = 2 … 12
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