參數(shù)資料
型號(hào)： SAB-XC167CI-16F20F
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP144
封裝： 0.50 MM PITCH, PLASTIC, TQFP-144
文件頁(yè)數(shù)： 62/80頁(yè)
文件大?。?/td> 2477K
代理商： SAB-XC167CI-16F20F
XC167
Derivatives
Timing Parameters
Data Sheet
61
V1.1, 2003-06
Preliminary
Bypass Operation
When bypass operation is configured (PLLCTRL = 0xB) the master clock is derived from
the internal oscillator (input clock signal XTAL1) through the input- and output-
prescalers:
fMC = fOSC / ((PLLIDIV+1)× (PLLODIV+1)).
If both divider factors are selected as ’1’ (PLLIDIV = PLLODIV = ’0’) the frequency of
fMC
directly follows the frequency of
fOSC so the high and low time of fMC is defined by the
duty cycle of the input clock
fOSC.
The lowest master clock frequency is achieved by selecting the maximum values for both
divider factors:
fMC = fOSC / ((3+1)× (14+1)) = fOSC / 60.
Phase Locked Loop (PLL)
When PLL operation is configured (PLLCTRL = 11B) the on-chip phase locked loop is
enabled and provides the master clock. The PLL multiplies the input frequency by the
factor F (
fMC = fOSC × F) which results from the input divider, the multiplication factor,
and the output divider (F = PLLMUL+1 / (PLLIDIV+1
× PLLODIV+1)). The PLL circuit
synchronizes the master clock to the input clock. This synchronization is done smoothly,
i.e. the master clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of
fMC is constantly adjusted so it
is locked to
fOSC. The slight variation causes a jitter of fMC which also affects the duration
of individual TCMs.
The timing listed in the AC Characteristics refers to TCPs. Because
fCPU is derived from
fMC, the timing must be calculated using the minimum TCP possible under the respective
circumstances.
The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCP is lower than
for one single TCP (see formula and Figure 16).
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler (K = PLLODIV+1) to generate the master clock signal
fMC. Therefore,
the number of VCO cycles can be represented as K
× N, where N is the number of
consecutive
fMC cycles (TCM).
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