
1999 Aug 05
7
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
7
PINNING INFORMATION
SYMBOL
PIN
DESCRIPTION
PIN TYPE
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
POM
OUT3_V
OUT3_I
OUT2_I
OUT2_V
V
SSA2
V
DDA2
VREFDA
OUT1_V
OUT1_I
OUT0_I
OUT0_V
EQOV
SYS_CLK
V
DDD5V1
V
SSD5V1
I
2
S_IN2_WS
I
2
S_IN2_DATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
not connected
not connected
not connected
not connected
not connected
not connected
not connected
power-on mute; timing determined by external capacitor
analog voltage output 3
analog current output 3
analog current output 2
analog voltage output 2
analog ground supply 2
analog supply voltage 2 (3 V)
voltage reference of the analog part
analog voltage output 1
analog current output 1
analog current output 0
analog voltage output 0
equalizer overflow line output
test pin output
digital supply voltage 1; peripheral cells only (3 or 5 V)
digital ground supply 1; peripheral cells only (3 or 5 V)
I
2
S-bus or LSB-justified format word select input from a digital audio source 2
I
2
S-bus or LSB-justified format left-right data input from a digital audio
source 2
I
2
S-bus clock or LSB-justified format input from a digital audio source 2
I
2
S-bus or LSB-justified format word select input from a digital audio source 1
I
2
S-bus or LSB-justified format left-right data input from a digital audio
source 1
I
2
S-bus clock or LSB-justified format input from a digital audio source 1
I
2
S-bus bit clock output for interface with DSP co-processor chip
I
2
S-bus input data channel 1 from DSP co-processor chip
I
2
S-bus input data channel 2 from DSP co-processor chip
I
2
S-bus word select output for interface with DSP co-processor chip
digital supply voltage 2; peripheral cells only (3 or 5 V)
digital ground supply 2; peripheral cells only (3 or 5 V)
I
2
S-bus output data channel 1 to DSP co-processor chip
I
2
S-bus output data channel 2 to DSP co-processor chip
digital input 1 of the DSP core (F0 of the status register)
AP2D
AP2D
AP2D
AP2D
AP2D
APVSS
APVDD
AP2D
AP2D
AP2D
AP2D
AP2D
B4CR
BT4CR
VDD5
VSS5
IBUFD
IBUFD
I
2
S_IN2_BCK
I
2
S_IN1_WS
I
2
S_IN1_DATA
26
27
28
IBUFD
IBUFD
IBUFD
I
2
S_IN1_BCK
I
2
S_IO_BCK
I
2
S_IO_IN1
I
2
S_IO_IN2
I
2
S_IO_WS
V
DDD5V2
V
SSD5V2
I
2
S_IO_OUT1
I
2
S_IO_OUT2
DSP_IN1
29
30
31
32
33
34
35
36
37
38
IBUFD
BT4CR
IBUFD
IBUFD
BT4CR
VDD5
VSS5
BT4CR
BT4CR
IBUFD