參數(shù)資料
型號(hào)： SAA7712
廠商： NXP Semiconductors N.V.
英文描述： Sound effects DSP
中文描述： DSP的音效
文件頁(yè)數(shù)： 21/44頁(yè)
文件大?。?/td> 178K
代理商： SAA7712
1999 Aug 05
21
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
8.6
I
2
C-bus control
8.6.1
I
NTRODUCTION
A general description of the I
2
C-bus format can be
obtained from Philips Semiconductors, International
Marketing and Sales Communications (IMSC).
For the external control of the SAA7712H a fast I
2
C-bus
is implemented. This is a 400 kHz bus which is downward
compatible with the standard 100 kHz bus.
There are different types of control instructions:
Instructions to control the DSP program, program the
coefficient RAM and read the values of parameters
Instructions to control the equalizer, program the
equalizer coefficient RAM to be able to change the
centre frequency, gain and Q-factor of the equalizer
sections
Instructions to control the source selection and
programmable parts, e.g. PLL clock speed.
The detailed description of the I
2
C-bus and commands is
given in the following sections. The description of the
different bits in the memory map is given in Section 9.6.
The equalizer cannot be used and cannot be
programmed if there is no word select and bit clock signal
present on a selected digital source input; see
audio_source bit in Table 3 (I
2
S_IN1 and I
2
S_IN2).
The minimum limit of the audio sample frequency is
determined by
1
18
f
SCL
.
8.6.2
C
HARACTERISTICS OF THE
I
2
C-
BUS
The I
2
C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must
be connected to V
DD
via a pull-up resistor when
connected to the output stages of a microcontroller. For a
400 kHz I
2
C-bus the recommendation from Philips
Semiconductors must be followed (e.g. up to loads of
200 pFonthebusapull-upresistorcanbeused,between
200 to 400 pF a current source or switched resistor must
be used). Data transfer can only be initiated when the bus
is not busy.
8.6.3
B
IT TRANSFER
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as control signals
(see Fig.11). The maximum clock frequency is 400 kHz.
To be able to run on this high frequency all the inputs and
outputs connected to this bus must be designed for this
high speed I
2
C-bus according to the Philips specification.
Fig.11 Bit transfer on the I
2
C-bus.
handbook, full pagewidth
MGS216
SDA
SCL
data line
stable;
data valid
change
of data
allowed
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