參數(shù)資料
型號(hào)： SAA7388GP
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： Error correction and host interface IC for CD-ROM ELM
中文描述： 8-BIT, 50.4 MHz, MICROCONTROLLER, PQFP80
文件頁(yè)數(shù)： 23/60頁(yè)
文件大?。?/td> 226K
代理商： SAA7388GP
1996 Apr 26
23
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (ELM)
SAA7388
7.7.24
ACMD
This read only register is only available in the ATAPI mode;
it is the ATAPI command register and is used to transfer
commands from the host to the SAA7388.
The CMDI interrupt is generated when;
The host writes to this register while the SAA7388 is the
selected drive (the DRV bit in the ADRSEL register is
equal to the RDRV bit in the DTCTR register)
The host writes the execute drive diagnostic command
(90H) to this register.
The BSY bit in the ASTAT register is also set under these
conditions. If the sub-CPU reads this register while CMDI
is asserted then it will be negated.
7.7.25
ADRADR
This write only register is the ATAPI Drive Address
register.
7.7.26
ASAMT
This register is the ATAPI Sector Number register.
7.7.27
ADCTR
This read only register is the ATAPI Device Control
register. If the SRSTI interrupt is asserted then reading this
register will negate it.
7.7.28
ADRSEL
Table 21
ADRSEL register bits
Bit 4 of this register is the DRV bit. When this bit is the same as the RDRV bit in the DTCTR register then the SAA7388
will be the selected ATAPI drive and will respond to host commands and produce host interrupts.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1
1
1
DRV
7.7.29
AINTR
This register is the ATAPI Interrupt Reason register.
7.7.30
AFEAT
This read only register is the ATAPI Features register.
7.7.31
AERR
This write only register is the ATAPI Error register.
7.7.32
DTCTR - D
ATA
T
RANSFER
C
ONTROL
R
EGISTER
The DTCTR register controls data transfer flows in the host
Interface block. On reset this register is cleared to all zeros
except for the RDRV bit which is set to logic 1. This means
that the SAA7388 will be set to drive 1 after a reset.
There are several possible data transfers through the
SAA7388 host Interface block and these are selected
using the TRANT bits. The transfers are described in the
Table 23.
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