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參數(shù)資料
| 型號： | SAA7388GP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Error correction and host interface IC for CD-ROM ELM |
| 中文描述： | 8-BIT, 50.4 MHz, MICROCONTROLLER, PQFP80 |
| 文件頁數(shù)： | 20/60頁 |
| 文件大?。?/td> | 226K |
| 代理商： | SAA7388GP |
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1996 Apr 26
20
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (ELM)
SAA7388
Table 14
RMOD bits
Note
1.
Where X = don’t care.
7.7.17
STAT3
Reading this register clears any DECI interrupts.
Table 15
STAT3 register bits
7.7.18
RESET
Writing to this register resets the SAA7388 and initializes all of the registers. The data written determines the host mode
of SAA7388.
Table 16
RESET register bits
The HSEL bits in the RESET register set the host interface mode. After a hardware reset the HSEL bits become 111.
The SAA7388 will then wait until the sub-CPU writes to the RESET register and selects the host mode. After hardware
reset 3-statable pins will be 3-state unless HRD is driven LOW.
RMOD3
RMOD2
RMOD1
RMOD0
MEANING
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
mode 0
mode 1
mode 2
mode 3
mode 4
mode 5
mode 6
mode 7
mode > 7 or error in mode byte (note 1)
BIT
NAME
MEANING
7
VALST
Registers associated with decoder interrupt valid = 0; Registers invalid = 1. This bit is
a valid/invalid flag for the registers related to the decoder interrupt. After decoder
interrupt, the sub-CPU must read out of all decoder registers before VALST goes
HIGH.
ECC not performed on current block = 0; ECC has been performed on current
block = 1. This bit will go to logic 1 if ECC correction has been performed on the
current block.
6
5
CBLK
2
1
0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
reserved
HSEL
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| SAA7388 | Error correction and host interface IC for CD-ROM ELM |
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