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參數(shù)資料
| 型號： | SAA7388GP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Error correction and host interface IC for CD-ROM ELM |
| 中文描述： | 8-BIT, 50.4 MHz, MICROCONTROLLER, PQFP80 |
| 文件頁數(shù)： | 18/60頁 |
| 文件大?。?/td> | 226K |
| 代理商： | SAA7388GP |
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1996 Apr 26
18
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (ELM)
SAA7388
7.7.14
STAT0
Resetting the chip clears all bits in this register.
Table 9
STAT0 register bits
7.7.15
STAT1
Resetting the chip clears all bits in this register.
The bits in this register indicate the reliability of data in the HEAD0 to HEAD3 registers. Bits MINERR, SECERR,
BLKERR and MODERR indicate errors in the minutes, seconds, frames and mode bytes in the header of the current
block. Bits SH0ERR to SH3ERR indicate errors in the respective bytes in the sub-header.
Table 10
STAT1 register bits
BIT
NAME
FUNCTION
7
CRCOK
Cyclic redundancy check not OK = 0; Cyclic redundancy check OK = 1. Set by the
EDC in accordance with the results of the CRC check.
Sync pattern detected at word count 0 to 1174 or 1176 onwards = 1. This bit is set to
logic 1 if the sync pattern in the incoming data is detected between word counts
0 and 1174 or 1176 to infinity, and the decoder has been retimed. Due to the
presence of the cache RAM, it is necessary to stop error correction also when long
blocks have been detected.
Sync pattern inserted by sync interpolator not coincident with data sync = 1. This bit
is set to logic 1, if the word counter reaches 1175 and no sync pattern has been
detected in the input data. It indicates that the sync interpolator circuit inserted a
sync.
With SYIEN = 0, no sync found. Data block size has been extended = 1. This bit is
set to logic 1, if the sync interpolator was switched off, and if the sync interpolator
indicated that sync insertion was necessary. This condition causes the block length to
be extended.
Reserved
Short block indication = 1. This bit is set to logic 1 if the decoder is not retimed when
a sync pattern is detected in an incorrect word location, and is ignored while the
SYDEN bit is set to logic 0.
One or more bytes of the block are flagged with C2 flags = 1. This bit is set to logic 1
if one or more bytes of the current block contain erasures as indicated by the C2PO
input.
Uncorrectable errors in block = 1. This bit is set to logic 1 when one or more bytes of
the current block remain in error after the error correction process.
6
ILSYNC
5
NOSYNC
4
LBLK
3
2
SBLK
1
ERABLK
0
UCEBLK
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MINERR
SECERR
BLKERR
MODER
SH0ERR
SH1ERR
SH2ERR
SH3ERR
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| SAA7388 | Error correction and host interface IC for CD-ROM ELM |
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