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參數(shù)資料
| 型號： | SAA7388GP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Error correction and host interface IC for CD-ROM ELM |
| 中文描述： | 8-BIT, 50.4 MHz, MICROCONTROLLER, PQFP80 |
| 文件頁數(shù)： | 14/60頁 |
| 文件大?。?/td> | 226K |
| 代理商： | SAA7388GP |
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1996 Apr 26
14
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (ELM)
SAA7388
7.7.4
IFSTAT
The IFSTAT register indicates the state of the host interface. In the ATAPI mode, only bits 7 to 2 have any meaning.
Table 4
IFSTAT register bits
BIT
NAME
DESCRIPTION
7
CMDI
Command interrupt. In the ATAPI mode this bit is asserted when the host has written
to the ATAPI command register (see ACMD register) and the drive is selected. It is
also asserted when the host writes the execute drive diagnostic command (90H) to
the ATAPI command register, regardless of whether the drive is selected. It is
negated when the sub-CPU reads the ACMD register. In the Sanyo and Oak
compatibility modes this bit is asserted while there are command bytes waiting in the
COMIN FIFO. It is negated when the COMIN FIFO is empty.
Data transfer end interrupt. This bit is asserted at the end of data transfer. It is
negated when the sub-CPU writes to the DTACK register. If the ATAPI mode is
selected this bit is also asserted when a program command has been received and
after a sub-CPU memory transfer.
Decoder interrupt. This bit is asserted when a new sector is available. It is negated by
reading the STAT3 register.
Subcode interrupt. This bit is asserted when a new subcode is available. It is negated
by reading the SUB_H register.
Data transfer busy. This bit indicates if a data transfer is taking place. It is asserted by
writing to the DTRG register and is negated at the end of the transfer.
SRST bit interrupt/status transfer busy. In the ATAPI mode this bit is asserted when
the host writes to the ATAPI device control register and sets the SRST bit. It is
negated when the sub-CPU reads the ADCTR register. It should be noted that if this
bit is asserted in the ATAPI mode then the sub-CPU interrupt will also be asserted.
The SRSTI interrupt cannot be disabled. In the Sanyo and Oak compatibility modes
this bit indicates if a status byte transfer is taking place. It is asserted by writing to the
SBOUT register and is negated when the host has emptied the status FIFO.
Data transfer and status transfer. These bits reflect the state of the DTEN and STEN
pins in the Sanyo and Oak compatibility modes. They are updated at the end of a
host read or write.
6
DTEI
5
DECI
4
SUBI
3
DTBSY
2
SRSTI/STBSY
1
0
DTEN
STEN
7.7.5
DBCL
AND
DBCH
The Data Byte Counter is used by the sub-CPU to control
the number of bytes that are transferred in a data transfer.
In the ATAPI mode all 16 bits are available while in the
Sanyo and Oak compatibility modes only 15 bits are
available with bit 7 of DBCH indicating the state of DTEI
(see Table 4). During memory-to-host data transfers the
data byte counter is decremented after every host read.
During host-to-memory data transfers the data byte
counter is decremented as data is written into external
buffer memory.
7.7.6
DACL, DACH
AND
DACHH
This 21-bit write-only register is used to specify the
external buffer address of the first byte of the data block to
be transferred to the host.
Once the address has been set, it is incremented
automatically as successive bytes are transferred with the
host. It should be noted that pointer operation is
asynchronous from host read/write operation. For this
reason, counter increments are not coincident with host
transfer operations.
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