參數(shù)資料
型號： SAA7388GP
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Error correction and host interface IC for CD-ROM ELM
中文描述： 8-BIT, 50.4 MHz, MICROCONTROLLER, PQFP80
文件頁數(shù)： 16/60頁
文件大小： 226K
代理商： SAA7388GP
1996 Apr 26
16
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (ELM)
SAA7388
7.7.12
CTRL0
Resetting the chip sets all the bits in this register to logic 0.
Table 6
CTRL0 register
BIT
NAME
FUNCTION
7
DECEN
Disable decoding = 0; Enable decoding = 1. This bit enables/disables decoding
functions. Disabling the decoding functions also disables the decoder interrupt.
At interrupt PT, header refer to current block = 0; At interrupt PT, header refer to next
block = 1. When this bit is set to logic 1 at decoder interrupt, CMA and header registers
will give information on the next block instead of on the current block. The lookahead
mode was included to provide support for bad RAMs, and to give the CPU better control
on the blocks it wants to read.
Disable error correction of bytes = 0; Enable correction of CIRC mis-corrections = 1.
Setting this bit to logic 0 instructs the error corrector not to correct bytes flagged as
reliable by the CIRC error corrector.
Disable automatic error correction = 0; Enable automatic error correction = 1. Requests
automatic extraction of form bit during mode2 correction from sub-header data.
Disable erasure flag use = 0; Enable erasure flag use = 1. When set to logic 1, the
SAA7388 will enable the use of erasure flag information for error correction. When set to
logic 0, the SAA7388 will disable the use of erasure flag information for error correction.
Use of erasure flags must be disabledSAA7388 when the CD-DSP does not output
erasure flags and when the internal buffer RAM is disabled (which is necessary for
repeat correction).
Disable data writes to the buffer and PTL updates = 0; Enables data writes to the buffer
and PTL updates = 1. This bit enables/disables writes from the CD drive into the buffer. It
also enables/disables pointer (PTL, PTH and PTHH) updates each time a block is
received. When WRRQ is set to logic 1, data write will start from the first byte of the next
block onwards. When WRRQ is set to logic 0, repeat correction is enabled. With WRRQ
set to logic 0, the internal buffer RAM is disabled.
Disable ECC correction = 0; Enable ECC correction = 1. When ECCRQ is set to logic 1
the blocks received by the SAA7388 will be error corrected before a decoder interrupt is
generated. When ECCRQ is set to logic 0 no corrections are performed. The algorithm
used is a QD, PD, QE, PE algorithm. In a first step, errors are corrected; in a second
step, erasures are corrected. Correction data is read from the on-chip 36 kbit buffer
memory.
Normal operation = 0; Test mode, do not use = 1, this bit must always be set to logic 0.
6
lookahead
5
E01RQ
4
AUTORQ
3
ERAMRQ
2
WRRQ
1
ECCRQ
0
ENCODE
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PDF描述
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