參數(shù)資料
型號(hào)： SAA6703AH
廠商： NXP SEMICONDUCTORS
元件分類： 顯示控制器
英文描述： CRT OR FLAT PNL GRPH DSPL CTLR, PQFP160
封裝： 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160
文件頁(yè)數(shù)： 9/97頁(yè)
文件大?。?/td> 488K
代理商： SAA6703AH
2004
Apr
01
17
Philips
Semiconductors
Product
specication
XGA
analog
input
at
panel
controller
SAA6703AH
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Table 9
Mode detection conguration registers (page 2); note 1
Note
1. X = don’t care.
ADC_G_CON
04H W
00H
adc_green_contrast[7:0]
ADC_B_BRI
05H W
00H
adc_blue_brightness[7:0]
ADC_B_CON
06H W
00H
adc_blue_contrast[7:0]
REGISTER
ADR R/W
RESET
D7
D6
D5
D4
D3
D2
D1
D0
Mode detection: 00H to 0EH
MD_CTRL
00H W
000 0000
no_vsync_
int_en
clear_int
int_lock
delay_
vsync
h_clocks_
accu
h_clocks_
cont
md_on
MD_INT_EN
01H W
0000 0000 jitter_int_en v_lines_
int_en
v_clocks_
int_en
h_clocks_
int_en
no_hsync_
int_en
vsync_int_
en
vsync_pol_
int_en
hsync_pol_
int_en
MD_POL
02H R
0 0011
jitter_
detected
vsync_pol
hsync_pol
no_vsync
no_hsync
MD_V_LINE_HI
03H R
000
v_lines[10:8]
MD_V_LINE_LO
04H R
00H
v_lines[7:0]
MD_H_CLK_HI
05H R
00H
h_clocks[15:8]
MD_H_CLK_LO
06H R
00H
h_clocks[7:0]
MD_V_CLK_HI
07H R
00H
v_clocks[23:16]
MD_V_CLK_MD
08H R
00H
v_clocks[15:8]
MD_V_CLK_LO
09H R
00H
v_clocks[7:0]
MD_INT_HI
0AH R
00 0000
vsync_int
jitter_int
vsync_pol_
int
hsync_pol_
int
no_vsync_
int
no_hsync_
int
MD_INT_LO
0BH R
000
v_lines_int
h_clocks_
int
v_clocks_
int
MD_ACT_INT
0CH R
X000 0000 reserved
reserved
asog_act_
int
acsvs_act_
int
avs_act_int ahs_act_int
MD_SYNC_ACT
0DH R
00 0000
reserved
asog_
active
acsvs_
active
avs_active
ahs_active
MD_ACT_IEN
0EH W
0000 0000 reserved
reserved
asog_int_
en
acsvs_int_
en
avs_int_en ahs_int_en
REGISTER
ADR R/W
RESET
D7
D6
D5
D4
D3
D2
D1
D0
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