參數(shù)資料
型號： SAA6703AH
廠商： NXP SEMICONDUCTORS
元件分類： 顯示控制器
英文描述： CRT OR FLAT PNL GRPH DSPL CTLR, PQFP160
封裝： 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160
文件頁數(shù)： 45/97頁
文件大小： 488K
代理商： SAA6703AH
2004
Apr
01
5
Philips
Semiconductors
Product
specication
XGA
analog
input
at
panel
controller
SAA6703AH
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5
BLOCK
DIA
GRAM
I2C-BUS
INTERFACE
configuration
data
CSG2/A0
SCL
SDA
CSG4/A1
TDO
INT
JTAG
INTERFACE
test control
signals
TRST
TMS
TDI
RST
TCK
50
51
157
155
156
154
153
41
42
23
127
55
CONTROL
UNIT
control signals
PA0 to PA7,
PB0 to PB7,
PC0 to PC7
58 to 65,
68, 69,
72 to 77,
80 to 87
52
53, 54, 126
138, 139
92 to 99,
104 to 111,
114 to 121
PD0 to PD7,
PE0 to PE7,
PF0 to PF7
OUTPUT
INTERFACE
INPUT
INTERFACE
DITHERING
UPSCALER
OSD
DOWN-
SCALER
RIN
VDDA(B)
VDDA(G)
VDDA(R)
VSSA(B)
VSSA(G)
VSSA(R)
SOGIN
HSYNC
VCLK
CLK
47
AGCANA
160
141
140
11
6
135
VSYNC
GIN
BIN
RBIAS
AUTO-
ADJUSTMENT
SAA6703AH
MODE
DETECTION
SYNC
SELECTION
AND CSYNC
DECODER
SYNC-
ON-
GREEN
SLICER
3
× ADC
n.c.
CLOCK GENERATOR:
PANEL CLOCK PLL
SAMPLE CLOCK PLL
PHASE SHIFT
COLOUR
LOOK-UP
TABLE
RGB data
3
× 10-bit
RGB data
3
× 8-bit
17
24
7
18
25
20
13
2
9
VDDA(IB)
8
VSSA(BIAS)(SOG)
10
27, 28, 30, 31,
33, 34, 36, 40,
136, 137, 148
RESERVED1 to
RESERVED8
37, 43, 44,
128, 129, 130,
133, 134
VSSD(EP1) to
VSSD(EP10)
48, 56, 66, 78,
88, 100, 112,
124, 131, 142
VDDD(EP1) to
VDDD(EP10)
49, 57, 67, 79,
89, 101, 113,
125, 132, 143
VDDA(EP)
VSSA(ADC)(R)
16
VSSA(ADC)(G)
5
VSSA(ADC)(B)
21
VDDA(ADC)(R)
14
VDDA(ADC)(G)
3
VDDA(ADC)(B)
19
VSSA(BIAS)(R)
1
VSSA(BIAS)(B)
12
VSSA(BIAS)(G)
159
VSSA(EP)
158
VSS(PLL)(P)
146
147
VSSA(PLL)(S)
149
VDDA(PLL)(S)
150
VDDD(PLL)(S)
152
VSSD(PLL)(S)
151
RGB data
3
× 8-bit
RGB data
3
× 8-bit
syncs
panel clock
sample clock
syncs
RGB data
3
× 6-bit or
3
× 8-bit
RGB data
3
× 6-bit or
3
× 8-bit
RGB data
3
× 6-bit or
3
× 8-bit
panel control
signals
mhc689
DECOUPLING
FIFO
PCLK
4
REF_B
15
REF_G
22
REF_R
26, 32, 38,
46, 71, 91,
103, 123,
145
VDDD(IC1) to
VDDD(IC9)
29, 35, 39,
45, 70, 90,
102, 122,
144
VSSD(IC1) to
VSSD(IC9)
CSG0, CSG1,
CSG3
OUTEN, PWM
VDD(PLL)(P)
Fig.1 Block diagram.
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