參數(shù)資料
型號(hào)： SAA6703AH
廠商： NXP SEMICONDUCTORS
元件分類： 顯示控制器
英文描述： CRT OR FLAT PNL GRPH DSPL CTLR, PQFP160
封裝： 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160
文件頁(yè)數(shù)： 4/97頁(yè)
文件大小： 488K
代理商： SAA6703AH
2004 Apr 01
12
Philips Semiconductors
Product specication
XGA analog input at panel controller
SAA6703AH
7
FUNCTIONAL DESCRIPTION
In this chapter detailed information for the general
configuration of the SAA6703AH is provided as well as
detailed background information belonging to certain
submodules of the device. Due to the high complexity of
the device functionality this section should be studied very
carefully.
7.1
Programming registers
7.1.1
CONFIGURATION PARAMETER MAPPING
The SAA6703AH operation is controlled by configuration
parameters, that can be multiple-bit words or consist of
only a single bit. The configuration parameters are
mapped to bits of the 8 bit I2C-bus programming registers,
that are accessible via the I2C-bus interface. Read-out
data such as measurement results or interrupt states is
mapped to readable I2C-bus registers.
The I2C-bus registers are organized in pages. Generally, a
register can only be accessed if the particular page is
activated with the exception of global registers, so
non-global registers are addressed by the I2C-bus
subaddress in combination with the matching active page,
but global registers are addressed by the subaddress
independently of the active page.
The global registers are mapped to I2C-bus subaddresses
F8H to FFH. The active page is defined by page_select at
subaddress FFH. In general, registers belonging to the
same functional unit are mapped onto the same page. The
I2C-bus register pages are shown in Table 2.
Table 2
I2C-bus register pages
7.1.2
I2C-BUS INTERFACE
The I2C-bus serial interface consists of two pins: the serial
clock pin SCL and the serial data pin SDA.
7.1.2.1
Transmission bit rate
The I2C-bus interface supports transmission speeds of up
to 3.4 Mbits/s, given that a minimum system clock rate is
provided. The required system clock rate depends on the
target I2C-bus bit rate, which is the clock rate applied to
pin SCL, and the spike suppression mode selected by
iic_spike_mode in register IIC_MODE (03H at page 0) as
shown in Table 3. If iic_spike_mode is set to 2, a high
oversampling rate is used and the most effective spike
suppression is provided.
Table 3
I2C-bus spike suppression modes
7.1.2.2
I2C-bus transmission timing
The SAA6703AH only operates as a slave and the clock
pin SCL is exclusively input. Data is transmitted and
received at I/O pin SDA. The SDA is an open-drain stage
with an external pull-up resistor. When a logic 0 is applied,
the bus is pulled to LOW-level by the output buffer. When
a logic 1 is applied, the output buffer switches to 3-state
and the pull-up resistor pulls the bus up to HIGH-level.
Data transfers are initiated by an I2C-bus master device by
sending the start condition, which is a change from
HIGH-to-LOW level at SDA when SCL is at HIGH-level
Data is transmitted byte wise. Data changes on SDA are
allowed only when SCL is at LOW-level and data is
sampled on the positive edge of SCL. The first transmitted
byte is the recipients I2C-bus device address and the data
transfer direction bit. All byte transfers are acknowledged
by the recipient by pulling SDA to LOW-level for the
following cycle.
PAGE
FUNCTIONAL UNIT
0
control unit and clock generator
1
ADC control
2
mode detection
3
auto-adjustment
4
input interface and picture generator
5
colour processing
6
decoupling FIFO
7
scalers
8
OSD
9
OSD colour denition
10
gamma correction and dithering
11
TFT output interface
iic_spike_
mode[1:0]
SYSTEM
CLOCK
DESCRIPTION
00
>6
× I2C-bus
bit rate
2-out-of-2 lter
01
>6
× I2C-bus
bit rate
2-out-of-3 majority lter
10
>16
× I2C-bus
bit rate
4-out-of-4 lter
11
not used
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