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參數(shù)資料
| 型號： | SAA6703AH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顯示控制器 |
| 英文描述： | CRT OR FLAT PNL GRPH DSPL CTLR, PQFP160 |
| 封裝： | 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160 |
| 文件頁數(shù)： | 71/97頁 |
| 文件大小： | 488K |
| 代理商： | SAA6703AH |
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2004 Apr 01
73
Philips Semiconductors
Product specication
XGA analog input at panel controller
SAA6703AH
7.16
Output interface
The Output Interface (OIF) provides picture data and
command signals to the display. Programming the output
interface, the output frame geometry can be defined.
As most displays require continuous data stream during
one frame or line, it is possible to define wait points. There
are different possibilities how to map the RGB data to the
output ports PA to PF.
The SAA6703AH does not have particular output ports for
panel signals VSYNC, HSYNC or DE. Instead, there are in
total 5 Configurable Signal Generator (CSG) outputs
which are driven by free programmable CSGs.
All output interface programming registers are mapped to
the I2C-bus configuration register page 11.
7.16.1
DEFINITION OF THE OUTPUT FRAME GEOMETRY
The total output frame area (main frame) is defined by
blank_line_length and last_line (registers OI_FX and
OI_FY). It consists of the visible data (active frame) and
The active frame is divided into border and picture area.
The picture area includes the data from the input stream.
The border area is around the picture area. If no border is
needed, the register values of picture and active area have
to be equal. The active frame can be put anywhere inside
the main frame except in the first row or in the first column
of the main frame.
The geometric values for the frames/areas depend on the
display and the timing. If the picture values are not correct
data may be lost or missing data will be replaced by border
colour. The serial output begins in the upper left corner of
the main frame in row 1 and column 1. The active frame
starts in row active_start_y and in column active_start_x
(point a in Fig.25). Values 0 are not allowed and the active
frame or the picture area cannot start in column one. The
picture area has to be contained in the active frame, at
maximum it may be identical to the active frame.
handbook, full pagewidth
MHC232
1,1
main frame
active frame
border area
picture area
last_line
blank_line_length
a
b
c
d
e
Fig.25 Output frame set-up.
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| SAA7157T-T | 29 MHz, VIDEO CLOCK GENERATOR, PDSO20 |
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| SAB-C163-16F25F | 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP100 |
| SAB-C165-L25F | 16-BIT, 14 MHz, MICROCONTROLLER, PQFP100 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA6712E | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA RGB to TFT graphics engine |
| SAA6713AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA analog input flat panel controller |
| SAA6713AH/V1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA analog input flat panel controller |
| SAA6713H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA dual input flat panel controller |
| SAA6713H/V1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA dual input flat panel controller |
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