參數(shù)資料
型號(hào)： SAA6703AH
廠商： NXP SEMICONDUCTORS
元件分類： 顯示控制器
英文描述： CRT OR FLAT PNL GRPH DSPL CTLR, PQFP160
封裝： 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160
文件頁數(shù)： 35/97頁
文件大小： 488K
代理商： SAA6703AH
2004 Apr 01
40
Philips Semiconductors
Product specication
XGA analog input at panel controller
SAA6703AH
handbook, full pagewidth
MHC214
÷2
CLK
PLL
clock
PRE-DIVIDER
pll_pre_div_en
pll_pre_div [15:0]
FREQUENCY
AND
PHASE
DETECTOR
OSCILLATOR
50 to 320 MHz
pll_en
m-DIVIDER
pll_m_div [1:0]
n-DIVIDER
pll_n_div [11:0]
Fig.7 PLL block diagram.
7.5
Synchronization pulse distribution
The line-locked PLL, input interface and mode detection
are provided with horizontal and vertical synchronization
pulse signals (HSYNC and VSYNC). Signal switching is
controlled by configuration registers SYNC_SEL (18H at
page 0) and SYNC_DIS (19H at page 0). A composite
sync decoder and hsync regeneration can be inserted.
Possible selections and the concerned configuration
parameters are shown in Fig.8 and described more
detailed in the Sections 7.5.1 to 7.5.5.
7.5.1
COMPOSITE SYNC INPUT
The composite sync decoder input is selected by sog_en
between the separated SOG provided by the
sync-on-green slicer and a composite sync applied at input
pin HSYNC (see Table 22). The sync-on-green slicer has
to be enabled by setting sync_on_green_en in register
ADC_CTRL (00H at page 1) to logic 1.
To provide a stable hsync during the vsync, the
sync-on-green slicer might have to be disabled during the
vsync which is performed automatically if sog_vs_disable
is set to logic 1; otherwise the sync-on-green slicer is
constantly enabled.
The composite sync decoder will regenerate hsync and
vsync signals for internal use. Figure 9 shows the
composite sync modes that can be used. The maximum
number of equalizing pulses (csync-3 and csync-4) may
not exceed 30.
Table 22 Composite sync decoder input selection
sog_en
CSYNC
1
SOG
0
HSYNC
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