參數(shù)資料
型號： SAA6703AH
廠商： NXP SEMICONDUCTORS
元件分類： 顯示控制器
英文描述： CRT OR FLAT PNL GRPH DSPL CTLR, PQFP160
封裝： 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160
文件頁數(shù)： 79/97頁
文件大小： 488K
代理商： SAA6703AH
2004 Apr 01
80
Philips Semiconductors
Product specication
XGA analog input at panel controller
SAA6703AH
Table 54 Global modes; note 1
Note
1. X = don’t care.
OI_
enable
power_
down
blank_
mode
MODE
ACTION
1
0
1
blank
all colours replaced by blank colour values
X
1
X
Power-down
all registers set to default, like soft reset; all outputs LOW
0
X
disable
all outputs reset but incoming data queued to trash
1
0
normal
normal operation
7.16.8
PANEL CLOCK
The output interface can handle single and double pixel
mode (bit double_pixel in register OI_CTRL1). In single
pixel mode one pixel (24 bits) is available each cycle at the
output ports. The panel clock PCLK is the same as the
back-end clock. In double pixel mode 2 pixels (48 bits) are
available at the output ports. The PCLK in double pixel
mode changes every second cycle of the back-end clock.
The panel clock polarity can be inverted by setting
PCLK_pol of register OI_CTRL1 to logic 1. At the
beginning of each frame the PCLK is synced again. It is
very important that the number of pixels in a double pixel
frame is even.
The horizontal sync signal of the VGA video input source
may be used as a reference clock for the panel PLL
(see Table 55). This allows more stable locking of the
panel timing to the source timing. In this mode the PLL will
be ‘coasted’ during vertical sync when a composite sync or
sync-on-green is enabled (iif_cs_sog_en = 1).
Table 55 Panel PLL
7.16.9
HOW TO START THE OUTPUT INTERFACE
Table 56 Starting output interface
7.16.10 PROGRAMMABLE OUTPUT DRIVE STRENGTH
For all data and control signals of the output interface
(PA[7:0], PB[7:0], PC[7:0], PD[7:0], PE[7:0], PF[7:0],
CSG[4:0], OUTEN and PWM) a programmable output
drive strength up to 15 mA is provided (in 8 steps and
starting at 2.9 mA); see Table 57.
For the PCLK output, a programmable output drive up to
30 mA is provided (in 8 steps and starting at 5.8 mA);
see Table 57.
Individual drive strength programming is possible for each
8-bit group of data signals (see Table 58). The drive
strength of control and clock signals are programmable
individually.
Table 57 Programmable drive strength
pll_src
FUNCTION
0
pre-divided clock
1
HS_PLL
STEP
ACTION
1
set-up frame geometry
2
set-up signal generators
3
set-up wait column and wait mode
4
set-up PCLK and pixel mode
5
enable output interface
DS2
DS1
DS0
DATA AND
CONTROL
OUTPUTS
(mA)
PCLK
OUTPUT
(mA)
0
2.9
5.8
0
1
3.4
6.8
010
4
8
011
5
10
100
6
12
101
8
16
1
0
11
22
1
15
30
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