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參數資料
| 型號： | SAA6703AH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顯示控制器 |
| 英文描述： | CRT OR FLAT PNL GRPH DSPL CTLR, PQFP160 |
| 封裝： | 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160 |
| 文件頁數： | 5/97頁 |
| 文件大?。?/td> | 488K |
| 代理商： | SAA6703AH |
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2004 Apr 01
13
Philips Semiconductors
Product specication
XGA analog input at panel controller
SAA6703AH
If the write mode was selected, the bus master sends a
byte containing the starting subaddress and then a series
of data bytes. In case the read mode was selected, the
addressed slave returns a series of data bytes. A read
transfer is preceded by a write transfer that transmits the
starting subaddress.
Data transfers are aborted by the stop condition, when
SDA is changed by the master from LOW-to-HIGH level
when SCL is at HIGH-level (see Fig.4).
7.1.2.3
I2C-bus device address
Bits A0 and A1 of the I2C-bus device address are
externally selected by two input pins CSG2/A0
and CSG4/A1. The device address (byte) of the
SAA6703AH is shown in Table 4.
Table 4
I2C-bus device address byte
The four possible I2C-bus device addresses are selected
via resistor strapping at pins CSG2/A0 and CSG4/A1
(see Table 5).
During the hardware reset (pin RST = LOW),
pins CSG2/A0 and CSG4/A1 are 3-stated. Their status at
the trailing edge of signal RST will latch and determine the
device address. Pull-up and pull-down resistors (4.7 k
suggested) select the address. An internal pull-down
resistance of approximately 100 k
is provided and
eliminates potentially the need for any external strapping
resistor. After reset, the pins carry the output of the
programmable signal generators.
Table 5
Device address selection
MSB
LSB
DEVICE ADDRESS BITS
R/W
01110
A1
A0
0/1
I2C-BUS DEVICE
ADDRESS
STRAPPING RESISTOR
PIN CSG4/A1
PIN CSG2/A0
70H
pull-down
72H
pull-down
pull-up
74H
pull-up
pull-down
76H
pull-up
Fig.3 Start of a data transfer.
handbook, full pagewidth
MHB248
SCL
SDA
A4
A1
A2
A3
A6
A5
ACK
R/W
A0
R5
R7
R6
START condition
acknowledge
Fig.4 End of a data transfer.
handbook, full pagewidth
MHB249
SCL
SDA
D7
D4
D5
D6
D1
D0
ACK
D2
D3
A/A
D1
D0
STOP condition
acknowledge/
not acknowledge
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