參數(shù)資料
型號： S80486-DX4-75-S-V-8-B
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 75 MHz, MICROPROCESSOR, PQFP208
封裝： SQFP-208
文件頁數(shù)： 67/69頁
文件大?。?/td> 1070K
代理商： S80486-DX4-75-S-V-8-B
7
AMD
PRELIMINARY
Enhanced Am486 Microprocessor
Figure 30 SMM Base Slot Offset ............................................................................................................. 48
Figure 31 SRAM Usage .......................................................................................................................... 48
Figure 32 SMRAM Location .................................................................................................................... 49
Figure 33 SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Through Mode
with Caching Enabled During SMM.......................................................................................... 50
Figure 34 SMM Timing in Systems Using Non-Overlaid Memory Spaces and Write-Back Mode with
Caching Enabled During SMM ................................................................................................. 50
Figure 35 SMM Timing in Systems Using Non-Overlaid Memory Spaces and Write-Back Mode with
Caching Disabled During SMM ................................................................................................ 50
Figure 36 SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode with
Caching Enabled During SMM ................................................................................................. 51
Figure 37 SMM Timing in Systems Using Overlaid Memory Spaces and Write-Through Mode with
Caching Disabled During SMM ................................................................................................ 51
Figure 38 SMM Timing in Systems Using Overlaid Memory Spaces and Configured in
Write-Back Mode...................................................................................................................... 51
Figure 39 CLK Waveforms ...................................................................................................................... 63
Figure 40 Output Valid Delay Timing ...................................................................................................... 63
Figure 41 Maximum Float Delay Timing .................................................................................................. 64
Figure 42 PCHK Valid Delay Timing ....................................................................................................... 64
Figure 43 Input Setup and Hold Timing ................................................................................................... 65
Figure 44 RDY and BRDY Input Setup and Hold Timing ........................................................................ 65
Figure 45 TCK Waveforms ...................................................................................................................... 66
Figure 46 Test Signal Timing Diagram .................................................................................................... 66
TABLES
Table 1
Clocking Options ....................................................................................................................... 1
Table 2
EADS Sample Time ................................................................................................................ 14
Table 3
Cache Line Organization ......................................................................................................... 19
Table 4
Legal Cache Line States ......................................................................................................... 19
Table 5
MESI Cache Line Status ......................................................................................................... 20
Table 6
Key to Switching Waveforms ................................................................................................... 22
Table 7
WBINVD/INVD Special Bus Cycles ......................................................................................... 33
Table 8
FLUSH Special Bus Cycles ..................................................................................................... 34
Table 9
Pin State during Stop Grant Bus State .................................................................................... 37
Table 10
SMRAM State Save Map ........................................................................................................ 43
Table 11
SMM Initial CPU Core Register Settings ................................................................................. 45
Table 12
Segment Register Initial States ............................................................................................... 45
Table 13
System Management Mode Revision Identifier ....................................................................... 46
Table 14
SMM Revision Identifier Bit Definitions ................................................................................... 46
Table 15
HALT Auto Restart Configuration ............................................................................................ 47
Table 16
I/O Trap Word Configuration ................................................................................................... 47
Table 17
Test Register (TR4) ................................................................................................................. 53
Table 18
Test Register (TR5) ................................................................................................................. 53
Table 19
CPU ID Codes ......................................................................................................................... 56
Table 20
CPUID Instruction Description ................................................................................................. 56
Table 21
Thermal Resistance (°C/W)
θ
JC and θJA for the Am486 CPU in 168-Pin PGA Package ......... 67
Table 22
Maximum TA at Various Airflows in °C .................................................................................... 67
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