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參數資料
| 型號： | S80486-DX4-75-S-V-8-B |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 75 MHz, MICROPROCESSOR, PQFP208 |
| 封裝： | SQFP-208 |
| 文件頁數： | 28/69頁 |
| 文件大小： | 1070K |
| 代理商： | S80486-DX4-75-S-V-8-B |
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Enhanced Am486 Microprocessor
AMD
34
PRELIMINARY
4.9.3
Snooping During Cache Flushing
As with snooping during normal operation, snooping is
permitted during a cache flush, whether initiated by the
FLUSH pin or WBINVD instruction. After completion of
the snoop, and write-back, if needed, the microproces-
sor completes the copy-back of modified cache lines.
4.10 Burst Write
The Enhanced Am486 microprocessor improves sys-
tem performance by implementing a burst write feature
Table 8. FLUSH Special Bus Cycles
A32–A2
M/IO D/C W/R BE3 BE2 BE1 BE0 Bus Cycle
0000 0001h
0
1
0
1
First Flush
Acknowledge
0000 0001h
0
1
0
1
Second
Flush
Acknowledge
for cache line write-backs and copy-backs. Standard
write operations are still supported because they are on
the Am486DX family of microprocessors. Burst writes
are always four 32-bit words and start at the beginning
of a cache line address of 0 for the starting access. The
timing of the BLAST and BRDY signals is identical to the
burst read. Figure 16 shows a burst write access. (See Figure
17 and Figure 18 for burst read and burst write access with
BOFF asserted.) In addition to using BLAST, the CACHE
signal indicates burstable cycles.
CACHE is a cycle definition pin used when in write-back
mode (CACHE floats in write-through mode). For pro-
cessor-initiated cycles, the signal indicates either
n for a read cycle, the internal cacheability of the cycle
n for a write cycle, a burst write-back or copy-back, if
KEN is asserted (for linefills).
W/R
BRDY
ADS
BLAST
ADR
M/IO
XX4
Data
XX0
XX4
XX8
XXC
Figure 16. Burst Write
CLK
CACHE
XXC
XX8
Data
to CPU
BRDY
BOFF
XX0
XX4
don’t care
ADR
XX0
ADS
BLAST
M/IO
W/R
CLK
XX4
XX8
XXC
XX4
XX8
XXC
Figure 17. Burst Read with BOFF Assertion
CACHE
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