- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98071 > S80486-DX4-75-S-V-8-B (ADVANCED MICRO DEVICES INC) 32-BIT, 75 MHz, MICROPROCESSOR, PQFP208 PDF資料下載
參數(shù)資料
| 型號： | S80486-DX4-75-S-V-8-B |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 75 MHz, MICROPROCESSOR, PQFP208 |
| 封裝： | SQFP-208 |
| 文件頁數(shù)： | 11/69頁 |
| 文件大?。?/td> | 1070K |
| 代理商： | S80486-DX4-75-S-V-8-B |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當(dāng)前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁
Enhanced Am486 Microprocessor
AMD
19
PRELIMINARY
memory coherency. The write-back cache requires en-
hanced system support because the cache may contain
data that is not identical to data in main memory at the
same address location.
4.5
Write-Back Cache Protocol
The Enhanced Am486 microprocessor family write-
back cache coherency protocol reduces bus activity
while maintaining data coherency in a multi-master en-
vironment. The cache coherency protocol offers the fol-
lowing advantages:
n No unnecessary bus traffic. The protocol dynamical-
ly identifies shared data to the granularity of a cache
line. This dynamic identification ensures that the traf-
fic on the external bus is the minimum necessary to
ensure coherency.
n Software-transparent. Because the protocol gives
the appearance of a single unified memory, software
does not have to maintain coherency or identify
shared data. Application software developed for a
system without a cache can run without modification.
Software support is required only in the operating
system to identify non-cacheable data regions.
A modified MESI protocol is implemented on the En-
hanced Am486 microprocessor family for systems with
write-back cache support. MESI allows cache line to
exist in four states: modified, exclusive, shared, and in-
valid. The Enhanced Am486 microprocessor family al-
locates memory in the cache due to a read miss. Write
allocation is not implemented. To maintain coherency
between cache and main memory, the MESI protocol
has the following characteristics:
n The system memory is always updated for the case
during a snoop when a modified line is hit.
n If a modified line is hit by another master during
snooping, the master is forced off the bus and the
snooped cache writes back the modified line to the
system memory. After the snooped cache completes
the write, the backed-off bus master restarts the ac-
cess and reads the modified data from memory.
4.5.1
Cache Line Overview
To implement the Enhanced Am486 microprocessor cache
coherency protocol, each tag entry is expanded to 2 bits: S1
and S0. Each tag entry is associated with a cache line. Table
3 shows the cache line organization.
Table 3. Cache Line Organization
Data Words (32 Bits)
Address Tag and Status
D0
Address Tag, S1, S0
D1
D2
D3
4.5.2
Line Status and Line State
A cache line can occupy one of four legal states as
indicated by bits S0 and S1. The line states are shown
in Table 4. Each line in the cache is in one of these
states. The state transition is induced either by the pro-
cessor or during snooping from an external bus master.
4.5.2.1
Invalid
An invalid cache line does not contain valid data for any
external memory location. An invalid line does not par-
ticipate in the cache coherency protocol.
4.5.2.2
Exclusive
An exclusive line contains valid data for some external
memory location. The data exactly matches the data in
the external memory location.
4.5.2.3
Shared
A shared line contains valid data for an external memory
location and the data is shared by another cache and
exactly matches the data in the external memory, or
indicates that the cache line is in write-through mode.
4.5.2.4
Modified
A modified line contains valid data for an external mem-
ory location. However, the data does not match the data
in the external location because the processor has mod-
ified the data since it was loaded from the external mem-
ory. A cache that contains a modified line is responsible
for ensuring that the data is properly maintained. This
means that in the case of an external access to that line
from another external bus master, the modified line is
first written back to the external memory before the other
external bus master can complete its access. Table 5
shows the MESI cache line states and the correspond-
ing availability of data.
Table 4. Legal Cache Line States
S1
S0
Line State
0
Invalid
0
1
Exclusive
1
0
Modified
1
Shared
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S80960SA-16 | 32-BIT, 16 MHz, RISC PROCESSOR, PQFP80 |
| S80960SB-10 | 32-BIT, 10 MHz, RISC PROCESSOR, PQFP80 |
| S80C186XL12 | 16-BIT, 12 MHz, MICROPROCESSOR, PQFP80 |
| S80C186XL25 | 16-BIT, 25 MHz, MICROPROCESSOR, PQFP80 |
| S80C186XL20 | 16-BIT, 20 MHz, MICROPROCESSOR, PQFP80 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S8049CR4 WAF | 制造商:Intel 功能描述: |
| S8049CRA4 WAF | 制造商:Intel 功能描述: |
| S804PV-M63 | 制造商:ABB Control 功能描述:S 800 PV-M 4pole 63A (1200V dc) MCB |
| S804PV-S10 | 制造商:ABB Control 功能描述:MCB S 800 PV-S 4 POLE 10A (800VDC) 制造商:ABB Control 功能描述:MCB, S 800 PV-S 4 POLE 10A (800VDC) |
| S804PV-S16 | 制造商:ABB Control 功能描述:MCB S 800 PV-S 4 POLE 16A (800VDC) 制造商:ABB Control 功能描述:MCB, S 800 PV-S 4 POLE 16A (800VDC) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。