參數(shù)資料
型號(hào)： S80486-DX4-75-S-V-8-B
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 75 MHz, MICROPROCESSOR, PQFP208
封裝： SQFP-208
文件頁(yè)數(shù)： 36/69頁(yè)
文件大小： 1070K
代理商： S80486-DX4-75-S-V-8-B
Enhanced Am486 Microprocessor
AMD
41
PRELIMINARY
tsu
thd
SMI Sampled
CLK
CLK2
SMI
RDY
Figure 24. SMI Timing for Servicing an I/O Trap
For uses such as fast enabling of external I/O devices, the
SMSAVE mode permits the restarting of the I/O instructions
and the HALT instruction. This is accomplished through I/O
Trap Restart and Halt Auto HALT Restart slots. Only I/O and
HALT opcodes are restartable. Attempts to restart any other
opcode may result in unpredictable behavior.
The System Management Interrupt hardware interface
consists of the SMI request input and the SMIACT output
used by the system to decode the SMRAM (see Figure 23).
7.3.1
System Management Interrupt Processing
SMI is a falling-edge triggered, non-maskable interrupt re-
quest signal. SMI is an asynchronous signal, but setup and
hold times must be met to guarantee recognition in a specific
clock. The SMI input does not have to remain active until the
interrupt is actually serviced. The SMI input needs to remain
active for only a single clock if the required setup and hold
times are met. SMI also works correctly if it is held active for
an arbitrary number of clocks (see Figure 24).
The SMI input must be held inactive for at least four clocks
after it is asserted to reset the edge-triggered logic. A subse-
quent SMI may not be recognized if the SMI input is not held
inactive for at least four clocks after being asserted. SMI, like
NMI, is not affected by the IF bit in the EFLAGS register
and is recognized on an instruction boundary. SMI does
not break locked bus cycles. SMI has a higher priority
than NMI and is not masked during an NMI. After SMI
is recognized, the SMI signal is masked internally until
the RSM instruction is executed and the interrupt ser-
vice routine is complete.
CPU
SMIACT
SMI
SMI Interface
}
Figure 23. Basic SMI Hardware Interface
Masking SMI prevents recursive calls. If another SMI
occurs while SMI is masked, the pending SMI is recog-
nized and executed on the next instruction boundary
after the current SMI completes. This instruction bound-
ary occurs before execution of the next instruction in the
interrupted application code, resulting in back-to-back
SMI handlers. Only one SMI signal can be pending while
SMI is masked. The SMI signal is synchronized inter-
nally and must be asserted at least three clock periods
prior to asserting the RDY signal to guarantee recogni-
tion on a specific instruction boundary. This is important
for servicing an I/O trap with an SMI handler.
7.3.2
SMI Active (SMIACT)
SMIACT indicates that the CPU is operating in SMM.
The CPU asserts SMIACT in response to an SMI inter-
rupt request on the SMI pin. SMIACT is driven active
after the CPU has completed all pending write cycles
(including emptying the write buffers), and before the
first access to SMRAM when the CPU saves (writes) its
state (or context) to SMRAM. SMIACT remains active
until the last access to SMRAM when the CPU restores
(reads) its state from SMRAM. The SMIACT signal does
not float in response to HOLD. The SMIACT signal is
used by the system logic to decode SMRAM. The num-
ber of clocks required to complete the SMM state save
and restore is dependent on system memory perfor-
mance. The values shown in Figure 25 assume 0 wait-
state memory writes (2 clock cycles), 2 – 1 – 1 – 1 burst
read cycles, and 0 wait-state non-burst reads (two clock
cycles). Additionally, it is assumed that the data read
during the SMM state restore sequence is not cache-
able. The minimum time required to enter a SMSAVE
SMI handler routine for the CPU (from the completion
of the interrupted instruction) is given by:
Latency to start of SMl handler = A + B + C = 161 clocks
and the minimum time required to return to the interrupt-
ed application (following the final SMM instruction be-
fore RSM) is given by:
Latency to continue application = E + F + G = 258 clocks
相關(guān)PDF資料
PDF描述
S80960SA-16 32-BIT, 16 MHz, RISC PROCESSOR, PQFP80
S80960SB-10 32-BIT, 10 MHz, RISC PROCESSOR, PQFP80
S80C186XL12 16-BIT, 12 MHz, MICROPROCESSOR, PQFP80
S80C186XL25 16-BIT, 25 MHz, MICROPROCESSOR, PQFP80
S80C186XL20 16-BIT, 20 MHz, MICROPROCESSOR, PQFP80
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S8049CR4 WAF 制造商:Intel 功能描述:
S8049CRA4 WAF 制造商:Intel 功能描述:
S804PV-M63 制造商:ABB Control 功能描述:S 800 PV-M 4pole 63A (1200V dc) MCB
S804PV-S10 制造商:ABB Control 功能描述:MCB S 800 PV-S 4 POLE 10A (800VDC) 制造商:ABB Control 功能描述:MCB, S 800 PV-S 4 POLE 10A (800VDC)
S804PV-S16 制造商:ABB Control 功能描述:MCB S 800 PV-S 4 POLE 16A (800VDC) 制造商:ABB Control 功能描述:MCB, S 800 PV-S 4 POLE 16A (800VDC)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*