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參數(shù)資料
| 型號(hào)： | S80486-DX4-75-S-V-8-B |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 75 MHz, MICROPROCESSOR, PQFP208 |
| 封裝： | SQFP-208 |
| 文件頁(yè)數(shù)： | 32/69頁(yè) |
| 文件大小： | 1070K |
| 代理商： | S80486-DX4-75-S-V-8-B |
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Enhanced Am486 Microprocessor
AMD
38
PRELIMINARY
Figure 20. Stop Clock State Machine
(valid for write-back mode only)
Figure 21. Recognition of Inputs when Exiting Stop Grant State
t20
t21
CLK
STPCLK
NMI
SMI
A
STPCLK
Sampled
Note: A = Earliest time at which NMI or SMI is recognized.
A RESET or SRESET brings the CPU from the Stop
Grant state to the Normal state. The CPU recognizes
the inputs required for cache invalidations (HOLD,
AHOLD, BOFF, and EADS) as explained later. The CPU
does not recognize any other inputs while in the Stop Grant
state. Input signals to theCPU are not recognized until 1 clock
after STPCLK is deasserted (see Figure 21).
While in the Stop Grant state, the CPU does not recog-
nize transitions on the interrupt signals (SMI, NMI, and
INTR). Driving an active edge on either SMI or NMI does not
guarantee recognition and service of the interrupt request fol-
lowing exit from the Stop Grant state. However, if one of the
interrupt signals (SMI, NMI, or INTR) is driven active while the
CPU is in the Stop Grant state, and held active for at least one
CLK after STPCLK is deasserted, the corresponding interrupt
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