參數(shù)資料
型號(hào)： S80486-DX4-75-S-V-8-B
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 75 MHz, MICROPROCESSOR, PQFP208
封裝： SQFP-208
文件頁(yè)數(shù)： 22/69頁(yè)
文件大?。?/td> 1070K
代理商： S80486-DX4-75-S-V-8-B
Enhanced Am486 Microprocessor
AMD
29
PRELIMINARY
Step 8 As an example, AHOLD is now removed. In the
next clock cycle, the current address of the
write-back access is driven onto the address
bus.
Step 9 The write-back access is finished when BLAST
and BRDY both transition to 0.
Step 10 In the clock cycle after the final write-back access,
the snooping cache drives HITM back to 1.
The status of the snooped and written-back line is now
either shared (INV = 0) or is changed to invalid (INV = 1).
4.8.6
Reordering of Write-Backs (AHOLD) with
BOFF
As seen previously, the Bus Interface Unit (BIU) com-
pletes the processor-initiated access first if the snooping
access occurs after the start of the processor-initiated
access. If the HITM signal occurs one clock cycle before
the ADS = 0 of the processor-initiated access, the write-back
receives priority and is executed first.
However, if the snooping access is executed after the
start of the processor-initiated access, there is a meth-
odology to reorder the access order. The BOFF signal
delays outstanding processor-initiated cycles so that a
snoop write-back can occur immediately (see Figure 13).
Scenario: If there are outstanding processor-initiated cy-
cles on the bus, asserting BOFF clears the bus pipeline. If
a snoop causes HITM to be asserted, the first cycle issued
by the microprocessor after deassertion of BOFF is the
write-back cycle. After the write-back cycle, it reissues the
aborted cycles. This translates into the following sequence:
Step 1 The processor starts a cacheable burst read
cycle.
Step 2 One clock cycle later, AHOLD is asserted. This
switches the address bus into an input one
clock cycle after AHOLD is asserted.
Step 3 Two clock cycles after AHOLD is asserted, the
EADS and INV signals are asserted to start the
snooping cycle.
Step 4 Two clock cycles after EADS is asserted, HITM
becomes valid. The line is modified, therefore
HITM = 0.
Step 5 Note that the processor-initiated access is not
completed because BLAST = 1.
Step 6 With HITM going Low, the core system logic as-
serts BOFF in the next clock cycle to the snooping
processor to reorder the access. BOFF overrides
BRDY. Therefore, the partial read is not used. It is
reread later.
Step 7 One clock cycle later BOFF is deasserted. The
write-back access starts one clock cycle later be-
cause the BOFF has cleared the bus pipeline.
Data
HITM
EADS
INV
Read
BRDY
AHOLD
BLAST
ADS
W/R
M/IO
ADR
CLK
W n+4
W n
W n+8
W n+C
Figure 12. Snoop Hit Cycle with Write-Back
Note: The circled numbers in this figure represent the steps in section 4.8.5.3.
1
7
8
9
5
4
6
3
2
CACHE
from CPU
to CPU
from CPU
相關(guān)PDF資料
PDF描述
S80960SA-16 32-BIT, 16 MHz, RISC PROCESSOR, PQFP80
S80960SB-10 32-BIT, 10 MHz, RISC PROCESSOR, PQFP80
S80C186XL12 16-BIT, 12 MHz, MICROPROCESSOR, PQFP80
S80C186XL25 16-BIT, 25 MHz, MICROPROCESSOR, PQFP80
S80C186XL20 16-BIT, 20 MHz, MICROPROCESSOR, PQFP80
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S8049CR4 WAF 制造商:Intel 功能描述:
S8049CRA4 WAF 制造商:Intel 功能描述:
S804PV-M63 制造商:ABB Control 功能描述:S 800 PV-M 4pole 63A (1200V dc) MCB
S804PV-S10 制造商:ABB Control 功能描述:MCB S 800 PV-S 4 POLE 10A (800VDC) 制造商:ABB Control 功能描述:MCB, S 800 PV-S 4 POLE 10A (800VDC)
S804PV-S16 制造商:ABB Control 功能描述:MCB S 800 PV-S 4 POLE 16A (800VDC) 制造商:ABB Control 功能描述:MCB, S 800 PV-S 4 POLE 16A (800VDC)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*