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參數(shù)資料
| 型號： | S71JL064H80BAI020 |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA73 |
| 封裝： | 11.60 X 8 MM, FBGA-73 |
| 文件頁數(shù)： | 40/95頁 |
| 文件大小： | 2244K |
| 代理商： | S71JL064H80BAI020 |
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February 25, 2004 S71JLxxxHxx_00A1
S29JL064H
45
Pre l i m i n a r y
trol signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available to
the system. ICC5 in the "DC Characteristics" section table represents the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The op-
eration that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at VIL but not within VSS±0.3 V, the standby current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a “0” (busy) until the internal reset operation is complete, which requires
a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/
BY# to determine whether the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing (RY/BY# pin is “1”), the reset
operation is completed within a time of tREADY (not during Embedded Algorithms).
The system can read data tRH after the RESET# pin returns to VIH.
Refer to the "AC Characteristics" section tables for RESET# parameters and to 15
for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins
are placed in the high impedance state.
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