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參數(shù)資料
| 型號(hào)： | S29PL127J70BFI000 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 8M X 16 FLASH 3V PROM, 70 ns, PBGA80 |
| 封裝： | 11 X 8 MM, LEAD FREE, FBGA-80 |
| 文件頁數(shù)： | 50/97頁 |
| 文件大?。?/td> | 3042K |
| 代理商： | S29PL127J70BFI000 |
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54
S29PL-J
S29PL-J_00_A10 September 7, 2007
Data
Sheet
(Adv an ce
Inf o r m a t io n)
13.7
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection
against inadvertent writes. In addition, the following hardware data protection measures prevent accidental
erasure or programming, which might otherwise be caused by spurious system level signals during VCC
power-up and power-down transitions, or from system noise.
13.7.1
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register and all internal program/erase circuits are disabled, and
the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The
system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater
than VLKO.
13.7.2
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE#, CE#, (CE1#, CE2# in PL129J) or WE# do not initiate a write
cycle.
13.7.3
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# (CE1# = CE2# in PL129J)= VIH or WE# =
VIH. To initiate a write cycle, CE# (CE1# / CE2# in PL129J) and WE# must be a logical zero while OE# is a
logical one.
13.7.4
Power-Up Write Inhibit
If WE# = CE# (CE1#, CE2# in PL129J) = VIL and OE# = VIH during power up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on
power-up.
14. Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows specific vendor-specified software algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data. The system can read CFI information at the addresses
given in Table 14.1 on page 55 to Table 14.4 on page 56. To terminate reading CFI data, the system must
write the reset command. The CFI Query mode is not accessible when the device is executing an Embedded
Program or embedded Erase algorithm.
The system can also write the CFI query command when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read CFI data at the addresses given in Table 14.1 to
Table 14.4. The system must write the reset command to return the device to reading array data.
For further information, please refer to the CFI Specification and CFI Publication 100. Contact your local sales
office for copies of these documents.
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相關(guān)代理商/技術(shù)參數(shù) |
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| S29PL127J70TAI130 | 制造商:Spansion 功能描述: 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 8MX16 70NS 56TSOP - Trays |
| S29PL127J70TFI130 | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 8MX16 70NS 56TSOP - Trays |
| S29PL127J70TFI131 | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 8MX16 70NS 56TSOP - Rail/Tube |
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| S29PL127J70TFI133 | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 8MX16 70NS 56TSOP - Tape and Reel |
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