參數(shù)資料
型號(hào): S29PL127J70BFI000
廠商: SPANSION LLC
元件分類: PROM
英文描述: 8M X 16 FLASH 3V PROM, 70 ns, PBGA80
封裝: 11 X 8 MM, LEAD FREE, FBGA-80
文件頁(yè)數(shù): 14/97頁(yè)
文件大小: 3042K
代理商: S29PL127J70BFI000
September 7, 2007 S29PL-J_00_A10
S29PL-J
21
Da ta
Sh e e t
(Adv a n ce
In f o r m ation)
8.
Pin Description
Note
Amax = A22 (PL127J), A21 (PL129J and PL064J), A20 (PL032J)
9.
Logic Symbol
Amax–A0
Address bus
DQ15–DQ0
16-bit data inputs/outputs/float
CE#
Chip Enable Inputs
OE#
Output Enable Input
WE#
Write Enable
VSS
Device Ground
NC
Pin Not Connected Internally
RY/BY#
Ready/Busy output and open drain.
When RY/BY#= VIH, the device is ready to accept read operations and commands. When RY/
BY#= VOL, the device is either executing an embedded algorithm or the device is executing a
hardware reset operation.
WP#/ACC
Write Protect/Acceleration Input.
When WP#/ACC= VIL, the highest and lowest two 4K-word sectors are write protected regardless
of other sector protection configurations. When WP#/ACC= VIH, these sector are unprotected
unless the DYB or PPB is programmed. When WP#/ACC= VHH, program and erase operations
are accelerated.
VIO
Input/Output Buffer Power Supply
(1.65 V to 1.95 V (for PL127J and PL129J) or 2.7 V to 3.6 V (for all PLxxxJ devices))
VCC
Chip Power Supply
(2.7 V to 3.6 V or 2.7 to 3.3 V)
RESET#
Hardware Reset Pin
CE1#, CE2#
Chip Enable Inputs.
CE1# controls the 64Mb in Banks 1A and 1B.
CE2# controls the 64 Mb in Banks 2A and 2B. (Only for PL129J)
max+1
16
DQ15–DQ0
Amax–A0
CE#
OE#
WE#
RESET#
RY/BY#
WP#/ACC
VIO (VCCQ)
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