參數(shù)資料
型號(hào)： S29PL127J70BFI000
廠商： SPANSION LLC
元件分類(lèi)： PROM
英文描述： 8M X 16 FLASH 3V PROM, 70 ns, PBGA80
封裝： 11 X 8 MM, LEAD FREE, FBGA-80
文件頁(yè)數(shù)： 18/97頁(yè)
文件大?。?/td> 3042K
代理商： S29PL127J70BFI000
September 7, 2007 S29PL-J_00_A10
S29PL-J
25
Da ta
Sh e e t
(Adv a n ce
In f o r m ation)
10.5
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. Note that during
automatic sleep mode, OE# must be at VIH before the device reduces current to the stated sleep mode
specification. ICC5 in DC Characteristics on page 73 represents the automatic sleep mode current
specification.
10.6
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in
progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current
will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is
completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the
RESET# pin returns to VIH.
Refer to the tables in AC Characteristic on page 74 for RESET# parameters and to Figure 20.5 on page 77
for the timing diagram.
10.7
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins (except for RY/BY#) are
placed in the highest Impedance state
Table 10.5 PL127J Sector Architecture (Sheet 1 of 7)
Bank
Sector
Sector Address (A22-A12)
Sector Size (Kwords)
Address Range (x16)
Ban
k
A
SA0
00000000000
4
000000h–000FFFh
SA1
00000000001
4
001000h–001FFFh
SA2
00000000010
4
002000h–002FFFh
SA3
00000000011
4
003000h–003FFFh
SA4
00000000100
4
004000h–004FFFh
SA5
00000000101
4
005000h–005FFFh
SA6
00000000110
4
006000h–006FFFh
SA7
00000000111
4
007000h–007FFFh
SA8
00000001XXX
32
008000h–00FFFFh
SA9
00000010XXX
32
010000h–017FFFh
SA10
00000011XXX
32
018000h–01FFFFh
SA11
00000100XXX
32
020000h–027FFFh
SA12
00000101XXX
32
028000h–02FFFFh
SA13
00000110XXX
32
030000h–037FFFh
SA14
00000111XXX
32
038000h–03FFFFh
SA15
00001000XXX
32
040000h–047FFFh
SA16
00001001XXX
32
048000h–04FFFFh
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