
I-46
EPSON
S1C88348/317/316/308 TECHNICAL HARDWARE
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control)
5.2.6 Control of system controller
Table 5.2.6.1 shows the control bits for the system controller.
Table 5.2.6.1(a) System controller control bits (MCU mode)
Note:
All the interrupts including NMI are disabled, until you write the optional value into both the "00FF00H" and
"00FF01H" addresses.
Address Bit
Name
00FF00
(MCU)
D7
D6
D5
D4
D3
D2
D1
D0
BSMD1
BSMD0
CEMD1
CEMD0
CE3
CE2
CE1
CE0
SR R/W
Function
Comment
Bus mode (CPU mode)
Chip enable mode
CE3 (R33)
CE2 (R32)
CE1 (R31)
CE0 (R30)
Only for 64K
bus mode
*1
In the Single chip
mode, these setting
are fixed at DC
output.
10
0
1
0
R/W
CE3 enable
CE2 enable
CE1 enable
CE0 enable
BSMD1
1
0
BSMD0
1
0
1
0
Mode
512K (Maximum)
512K (Minimum)
64K
Single chip
CEMD1 CEMD0
CE signal output
DC (R3x) output
CE signal output Enable/Disable
Enable:
Disable:
CE3 disable
CE2 disable
CE1 disable
CE0 disable
64K (CE0)
32K (CE0, CE1)
16K
(CE0–CE3...S1C88308)
(CE1–CE3...S1C88316)
8K (CE0–CE3)
1
0
1
0
1
0
00FF01 D7
D6
D5
D4
D3
D2
D1
D0
SPP7
SPP6
SPP5
SPP4
SPP3
SPP2
SPP1
SPP0
Stack pointer page address
< SP page allocatable address >
Single chip mode:
64K mode:
512K (min) mode:
512K (max) mode:
0
R/W
1
0
(MSB)
(LSB)
only 0 page
0–27H page
00FF02
D7
D6
D5
D4
D3
D2
D1
D0
EBR
WT2
WT1
WT0
CLKCHG
OSCC
VDC1
VDC0
Bus release enable register
(K11 and R51 terminal specification)
Wait control register
CPU operating clock switch
OSC3 oscillation On/Off control
Operating mode selection
*2
*1 This is just R/W register on S1C88348/317.
*2 This is just R/W register on S1C88308.
0
R/W
BREQ
BACK
OSC3
On
WT2
1
0
WT1
1
0
1
0
Number
of state
14
12
10
8
6
4
2
No wait
Input port
Output port
OSC1
Off
K11
R51
VDC1
1
0
VDC0
×
1
0
High speed (VD1=3.3V)
Low power (VD1=1.3V)
Normal
(VD1=2.2V)
WT0
1
0
1
0
1
0
1
0
Mode
Operating mode