
II-98
EPSON
S1C88348/317/316/308 TECHNICAL SOFTWARE
16 SVD (SUPPLY VOLTAGE DETECTION) CIRCUIT
16 SVD (SUPPLY VOLTAGE DETECTION) CIRCUIT
Specifications
Control of SVD circuit
(1) svd_auto: Supply voltage detection in 1/4 Hz auto sampling mode
After setting the 1/4 Hz auto-sampling mode to turn the SVD circuit ON, reads out SVD detection
data into the A register.
(2) svd_continue: Supply voltage detection in continuously sampling mode
Sets the continuous sampling mode (cancels the 1/4 Hz auto-sampling mode) to turn the SVD
circuit ON, and reads out SVD detection data into A register after calling a delay routine.
Flowchart
(1) Supply voltage detection
(2) Supply voltage detection
in 1/4 Hz auto sampling mode
in continuously sampling mode
I/O Map
svd_auto_init
1/4 Hz auto-sampling on
SVD on
ret
svd_continue
Masks except for detection data
1/4 Hz auto-sampling off
SVD on
svd_delay
Reads SVD data FF12H
A register
← data (lower 4 bits)
svd_off
ret
svd_auto_read
Masks except for detection data
Reads SVD data FF12H
A register
← data (lower 4 bits)
ret
Address Bit
Name
SR R/W
Function
Comment
10
00FF12 D7
D6
D5
D4
D3
D2
D1
D0
–
SVDSP
SVDON
SVD3
SVD2
SVD1
SVD0
–
SVD auto-sampling control
SVD continuous sampling control/status
SVD detection level
Constantry "0" when
being read
These registers are
reset to "0" when
SLP instruction
is executed.
*2
–
0
1
→0*1
0
X
R/W
R
–
On
Busy
On
–
Off
Ready
Off
R
W
SVD3
1
:
0
SVD2
1
:
0
SVD1
1
:
0
SVD0
1
0
:
0
Detection level
Level 15
Level 14
:
Level 0
*1 After initial reset, this status is set "1" until conclusion of hardware first sampling.
*2 Initial values are set according to the supply voltage detected at first sampling by hardware.
Until conclusion of first sampling, SVD0–SVD3 data are undefined.