
II-66
EPSON
S1C88348/317/316/308 TECHNICAL SOFTWARE
12 PROGRAMMABLE TIMER
(Invalid)
Specifications
Vector address setting for programmable timer interrupt
(2) timer1ch_init, pt0_intr: Initialization and interrupt processing for 16-bit one-shot timer
(one channel)
This is an example of using the programmable timer as a 16-bit x 1 system one-shot timer and
performs the following settings:
Count mode
16-bit x 1
Pulse output channel
Timer 0
Pulse external (TOUT) output
OFF
<Timer 0>
Timer mode
Programmable timer (one-shot mode)
Count clock
fOSC3 x 1/4
Reload data
33,200 (= 33.2 msec, when fOSC3 is 4 MHz)
<Timer 1>
Cannot be used
After setting the above, it enables the timer 1 interrupt, and starts the timer.
The interrupt level has been set at IRQ3 and an interrupt is generated 33.2 msec after starting.
Vector address setting for programmable timer interrupt
(3) evcnt_init, pt1_intr, evcnt_intr: Initialization and interrupt processing for 8-bit event counter
This is an example of using the programmable timer as an 8-bit event counter and 8-bit reload
timer, and performs the following settings:
Count mode
8-bit x 2
Pulse output channel
Timer 0
Pulse external (TOUT) output
OFF
<Timer 0>
Timer mode
Event counter (reload mode)
Input clock
K10 with noise rejector
Count timing
Falling edge
Reload data
0FFH (Event counter initial value)
<Timer 1>
Timer mode
Programmable timer (reload mode)
Count clock
fOSC3 x 1/64
Reload data
250 (= 4 msec, when fOSC3 is 4 MHz)
After setting the above, it enables the the event counter and timer 1 interrupts, and starts each
timer.
The interrupt level has been set at IRQ3 and an interrupt is generated by the overflow of the event
counter or timer 1.
Timer 1 is programmed to generate an interrupt in 4 msec cycles. This example reads the event
counter data in the interrupt processing routine and calculates the difference between it and
previous count value. This difference is made to the number of clocks that had been input in the 4
msec period.
K10 input
Event counter
Timer 1 interrupt
FFH FEH FDH FCH FBH FAH F9H
Start
4 msec
FFH - FCH = 3
FCH - F9H = 3
Fig. 12.1 Event counter processing