
S1C88348/317/316/308 TECHNICAL SOFTWARE
EPSON
II-111
APPENDIX A TABLE OF INPUT/OUTPUT PORT TERMINALS
Appendix A
Table of Input/Output Port Terminals
CPU
mode
Bus
mode
K00~07
K10
K11
R
00~07
R10~17
R20~22
R23
R24
(Initial
setting)
CE0
output
(invalid)
CE1
output
(invalid)
CE2
output
(invalid)
CE3
output
(invalid)
Bus
release
Serial
interface
Comparator
0
Comparator
1
CL
output
FR
output
TOUT
output
FOUT
output
BZ
output
Single
chip
Expanded
64K
Expanded
512K
(MIN
&
MAX)
MCU
Input
port
terminals
Special
output
R25
R26
R27
R30
R31
R32
R33
R34
R35~37
R50
R51
P00~07
P10
P11
P12
P13
P14
P15
P16
P17
Output
port
terminals
I/O
port
terminals
K00~07
K10
K
11
↑
BREQ
R00~07
R10~17
R20~22
R23
R24
R25
R26
R27
R30
R31
R32
R33
R34
R35~37
R50
R51
↑
CL
FR
TOUT
FOUT
BZ
BACK
P00~07
P10
P11
P12
P13
P14
P15
P16
P17
↑
S
IN
SOUT
SCLK
S
R
D
Y
CMPP0
CMPM0
CMPP1
CMPM1
(No
special
output)
CE0
output
CE1
output
CE2
output
CE3
output
Bus
release
Serial
interface
Comparator
0
Comparator
1
CL
output
FR
output
TOUT
output
FOUT
output
BZ
output
K00~07
K10
K
11
↑
BREQ
A0~7
A8~15
R20~22
RD
WR
R25
R
26
R27
R
30
R31
R
32
R33
R
34
R35~37
R50
R
51
↑
CL
FR
TOUT
FOUT
BZ
BACK
D0~7
P10
P11
P12
P13
P14
P15
P16
P17
↑
S
IN
SOUT
SCLK
S
R
D
Y
CMPP0
CMPM0
CMPP1
CMPM1
(No
special
output)
CE0
output
CE1
output
CE2
output
CE3
output
Bus
release
Serial
interface
Comparator
0
Comparator
1
CL
output
FR
output
TOUT
output
FOUT
output
BZ
output
K00~07
K10
K
11
↑
BREQ
A0~7
A8~15
A16~18
RD
WR
R25
R
26
R27
R
30
R31
R
32
R33
R
34
R35~37
R50
R
51
↑
CL
FR
TOUT
FOUT
BZ
BACK
D0~7
P10
P11
P12
P13
P14
P15
P16
P17
↑
S
IN
SOUT
SCLK
S
R
D
Y
CMPP0
CMPM0
CMPP1
CMPM1
CE0
CE1
CE2
CE3
CE0
CE1
CE2
CE3
Terminal
configuration
depending
on
model
S1C88308
S1C88348 S1C88317 S1C88316
P00~07
D0~7
P10
SIN
P11
P12
SCLK
P13
P
14
P15
P
16
P17
↑
↑↑↑↑
↑↑↑
R27
TOUT
R30
CE0
R31
CE1
R32
CE2
R33
CE3
R34
FOUT
R35~37
R50
BZ
R51
BACK
↑↑↑↑↑↑
↑
R00~07
A0~7
R10~17
A8~15
R20~22
A16~18
R23
RD
R24
WR
R25
CL
R26
FR
↑
↑↑↑↑
K00~07
K10
EVIN
K11
BREQ
↑↑
SOUT
SRDY
CMPP0
CMPM0
CMPP1
CMPM1