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參數(shù)資料
| 型號： | S1C60N05D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC53 |
| 封裝： | DIE-53 |
| 文件頁數(shù)： | 63/95頁 |
| 文件大小： | 736K |
| 代理商： | S1C60N05D0A0100 |
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69
7674F–AVR–09/09
ATmega164P/324P/644P
Bit 1 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
11.2.6
PCMSK3 – Pin Change Mask Register 3
Bit 7:0 – PCINT31:24: Pin Change Enable Mask 31:24
Each PCINT31:24-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT31:24 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT31..24 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
11.2.7
PCMSK2 – Pin Change Mask Register 2
Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23..16
Each PCINT23:16-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT23:16 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT23..16 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
11.2.8
PCMSK1 – Pin Change Mask Register 1
Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15..8
Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O
pin is disabled.
Bit
7
6
543
210
PCINT31
PCINT30
PCINT29
PCINT28
PCINT27
PCINT26
PCINT25
PCINT24
PCMSK2
Read/Write
R/W
Initial Value
0
Bit
7
6
543
210
PCINT23
PCINT22
PCINT21
PCINT20
PCINT19
PCINT18
PCINT17
PCINT16
PCMSK2
Read/Write
R/W
Initial Value
0
Bit
7
65
43
210
PCINT15
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
PCINT9
PCINT8
PCMSK1
Read/Write
R/W
Initial Value
0
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