參數(shù)資料
型號： S1C60N05D0A0100
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, UUC53
封裝： DIE-53
文件頁數(shù)： 60/95頁
文件大?。?/td> 736K
代理商： S1C60N05D0A0100
66
7674F–AVR–09/09
ATmega164P/324P/644P
11. External Interrupts
11.1
Overview
The External Interrupts are triggered by the INT2:0 pin or any of the PCINT31:0 pins. Observe
that, if enabled, the interrupts will trigger even if the INT2:0 or PCINT31:0 pins are configured as
outputs. This feature provides a way of generating a software interrupt.
The Pin change interrupt PCI3 will trigger if any enabled PCINT31:24 pin toggle, Pin change
interrupt PCI2 will trigger if any enabled PCINT23:16 pin toggles, Pin change interrupt PCI1 if
any enabled PCINT15:8 toggles and Pin change interrupts PCI0 will trigger if any enabled
PCINT7:0 pin toggles. PCMSK3, PCMSK2, PCMSK1 and PCMSK0 Registers control which pins
contribute to the pin change interrupts. Pin change interrupts on PCINT31:0 are detected asyn-
chronously. This implies that these interrupts can be used for waking the part also from sleep
modes other than Idle mode.
The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up
as indicated in the specification for the External Interrupt Control Registers – EICRA (INT2:0).
When the external interrupt is enabled and is configured as level triggered, the interrupt will trig-
ger as long as the pin is held low. Low level interrupts and the edge interrupt on INT2:0 are
detected asynchronously. This implies that these interrupts can be used for waking the part also
from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle
mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
11.2
Register Description
11.2.1
EICRA – External Interrupt Control Register A
The External Interrupt Control Register A contains control bits for interrupt sense control.
Bits 7:6 – Reserved
These bits are reserved in the ATmega164P/324P/644P, and will always read as zero.
Bits 5:0 – ISC21, ISC20 – ISC00, ISC00: External Interrupt 2 - 0 Sense Control Bits
The External Interrupts 2 - 0 are activated by the external pins INT2:0 if the SREG I-flag and the
corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that
activate the interrupts are defined in Table 11-1. Edges on INT2..INT0 are registered asynchro-
nously. Pulses on INT2:0 pins wider than the minimum pulse width will generate an interrupt.
Shorter pulses are not guaranteed to generate an interrupt.
Bit
76543210
–
ISC21
ISC20
ISC11
ISC10
ISC01
ISC00
EICRA
Read/Write
R
R/W
Initial Value
00000000
相關(guān)PDF資料
PDF描述
S1C621A0F0A0100 MICROCONTROLLER, PQFP80
S1C63158D0A010P 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53
S1C7XXXF00E199 16-BIT, 90 MHz, RISC MICROCONTROLLER, PQFP
S2041 PHOTO TRANSISTOR DETECTOR
S3P44R10 TRIGGER OUTPUT SOLID STATE RELAY, 4000 V ISOLATION-MAX
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S1C60N08 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer
S1C60N16 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer
S1C60R08 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer
S1C63004 制造商:EPSON 制造商全稱:EPSON 功能描述:CMOS 4-bit Single Chip Microcontroller
S1C63008 制造商:EPSON 制造商全稱:EPSON 功能描述:CMOS 4-bit Single Chip Microcontroller
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*