參數(shù)資料
型號(hào)： S1C60N05D0A0100
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, UUC53
封裝： DIE-53
文件頁數(shù)： 21/95頁
文件大?。?/td> 736K
代理商： S1C60N05D0A0100
S1C60N05 TECHNICAL MANUAL
EPSON
11
CHAPTER 3: CPU, ROM, RAM
CPU, ROM, RAM
CPU
The S1C60N05 Series employs the S1C6200B core CPU, so
that register configuration, instructions, and so forth are
virtually identical to those in other processors in the family
using the S1C6200B. Refer to the "S1C6200/6200A Core
CPU Manual" for details of the S1C6200B.
Note the following points with regard to the S1C60N05
Series:
(1) The SLEEP operation is not provided, so the SLP instruc-
tion cannot be used.
(2) Because the ROM capacity is 1,536 words, 12 bits per
word, bank bits are unnecessary, and PCB and NBP are
not used.
(3) The RAM page is set to 0 only, so the page part (XP, YP)
of the index register that specifies addresses is invalid.
PUSH
XP
PUSH
YP
POP
XP
POP
YP
LD
XP,r
LD
YP,r
LD
r,XP
LD
r,YP
CHAPTER 3
3.1
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