參數(shù)資料
型號(hào)： S1C60N05D0A0100
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, UUC53
封裝： DIE-53
文件頁(yè)數(shù)： 32/95頁(yè)
文件大?。?/td> 736K
代理商： S1C60N05D0A0100
40
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
10. I/O Ports
10.1
Overview
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that
the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the
SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/dis-
abling of pull-up resistors. Each output buffer has symmetrical drive characteristics with both high sink and source
capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable
pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both V
CC and
Ground as indicated in Figure 10-1 on page 40. See “Electrical Characteristics” on page 115 for a complete list of
parameters.
Figure 10-1. I/O Pin Equivalent Schematic
All registers and bit references in this section are written in general form. A lower case “x” represents the number-
ing letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit
defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here docu-
mented generally as PORTxn. The physical I/O Registers and bit locations are listed in “Register Description” on
Four I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data
Direction Register – DDRx, Pull-up Enable Register – PUEx, and the Port Input Pins – PINx. The Port Input Pins
I/O location is read only, while the Data Register, the Data Direction Register, and the Pull-up Enable Register are
read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit
in the Data Register.
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page 41. Most port pins
are multiplexed with alternate functions for the peripheral features on the device. How each alternate function inter-
feres with the port pin is described in “Alternate Port Functions” on page 45. Refer to the individual module sections
for a full description of the alternate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port
as general digital I/O.
C
pin
Logic
R
pu
See Figure
"General Digital I/O" for
Details
Pxn
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