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參數(shù)資料
| 型號： | S1C60N05D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC53 |
| 封裝： | DIE-53 |
| 文件頁數(shù)： | 30/95頁 |
| 文件大?。?/td> | 736K |
| 代理商： | S1C60N05D0A0100 |
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39
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
9.3.4
PCICR – Pin Change Interrupt Control Register
Bits 7:1 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit 0 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is
enabled. Any change on any enabled PCINT3..0 pin will cause an interrupt. The corresponding interrupt of Pin
Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT3..0 pins are enabled individually by
the PCMSK Register.
9.3.5
PCIFR – Pin Change Interrupt Flag Register
Bits 7:1 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT3..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in
SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
9.3.6
PCMSK – Pin Change Mask Register
Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bits 3:0 – PCINT3..0: Pin Change Enable Mask 3..0
Each PCINT3..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT3..0 is
set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT3..0 is
cleared, pin change interrupt on the corresponding I/O pin is disabled.
Bit
7
65
43
2
1
0
–
PCIE0
PCICR
Read/Write
RRR
RR
R/W
Initial Value
0
Bit
7
65
43
2
1
0
–
PCIF0
PCIFR
Read/Write
RRR
RR
R/W
Initial Value
0
Bit
765
432
10
–
PCINT3
PCINT2
PCINT1
PCINT0
PCMSK
Read/Write
R
R/W
Initial Value
000
00
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