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參數(shù)資料
| 型號(hào)： | S1C60N05D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC53 |
| 封裝： | DIE-53 |
| 文件頁(yè)數(shù)： | 43/95頁(yè) |
| 文件大?。?/td> | 736K |
| 代理商： | S1C60N05D0A0100 |
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50
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
Notes:
1. EXT_CLOCK is 1 when external clock is selected as main clock.
10.4
Register Description
10.4.1
PORTCR – Port Control Register
Bits 7:2, 0 – Reserved
These bits are reserved and will always read zero.
Bit 1 – BBMB: Break-Before-Make Mode Enable
When this bit is set the Break-Before-Make mode is activated for the entire Port B. The intermediate tri-state cycle
is then inserted when writing DDRxn to make an output. For further information, see “Break-Before-Make Switch-
10.4.2
PUEB – Port B Pull-up Enable Control Register
Table 10-5.
Overriding Signals for Alternate Functions in PB1..PB0
Signal
Name
PB1/ADC1/AIN1/OC0B/CLKI/ICP0/PCINT1
PB0/ADC0/AIN0/OC0A/PCINT0
PUOE
EXT_CLOCK(1)
0
PUOV
0
DDOE
EXT_CLOCK(1)
0
DDOV
0
PVOE
EXT_CLOCK(1) + OC0B Enable
OC0A Enable
PVOV
EXT_CLOCK(1) OC0B
OC0A
PTOE
0
DIEOE
EXT_CLOCK(1) + (PCINT1 PCIE0) +
ADC1D
(PCINT0 PCIE0) + ADC0D
DIEOV
(EXT_CLOCK(1) PCINT1 PCIE0)
PCINT0 PCIE0
DI
CLOCK/ICP0/PCINT1 Input
PCINT0 Input
AIO
ADC1/Analog Comparator Negative Input
ADC0/Analog Comparator Positive Input
Bit
7
6
5
4
3
2
1
0
–
BBMB
–PORTCR
Read/Write
R
R/W
R
Initial Value
0
Bit
765
432
10
–
PUEB3
PUEB2
PUEB1
PUEB0
PUEB
Read/Write
R
R/W
Initial Value
000
00
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