參數(shù)資料
型號(hào): S-4561A
元件分類: 顯示控制器
英文描述: 16 X 60 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC166
封裝: 7.65 X 2 MM, DIE-166
文件頁(yè)數(shù): 47/48頁(yè)
文件大?。?/td> 427K
代理商: S-4561A
LCD Controller-Driver
S-4561A
8
Seiko Instruments Inc.
Figure 5 4-Bit Length Parallel Interface (68-Family CPU)
Remarks:
RIn case of a 4-bit length interface, data is transmitted through the four buses DB4 to DB7 (buses DB0 to DB3
are not used. Set DB0 to DB3 “Open”).
RThe data transmission to the CPU is completed by transmitting 4-bit data twice. The data transmission is
executed in the order from upper 4 bits to lower 4 bits. The upper 4 bits of data immediately after the output
level of the RS pin changes are transmitted. Leave the RS pin unchanged until lower bits finish the data
transmission.
E
RS
[Example: 4-Bit Length Parallel Interface] (68-Family CPU)
I3
I7
I2
I6
I1
I5
AC3
AC2
AC1
AC0
D7
D6
D5
D4
Busy
D3
0
D2
AC5
D1
AC4
D0
I0
I4
Upper
Lower
Upper
Lower
R/WX
DB7
DB6
DB5
DB4
BUSY Flag, Address Counter Read
Data Read
Write Instruction
E (RD)
RS
I3
I7
I2
I6
I1
I5
AC3
AC2
AC1
AC0
D7
D6
D5
D4
Busy
D3
0
D2
AC5
D1
AC4
D0
I0
I4
Upper
Lower
Upper
Lower
R/WX (WR)
DB7
DB6
DB5
DB4
Write Instruction
Data Read
BUSY Flag, Address Counter Read
[Example: 4-Bit Length Parallel Interface] (80-Family CPU)
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