參數(shù)資料
型號: S-4561A
元件分類: 顯示控制器
英文描述: 16 X 60 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC166
封裝: 7.65 X 2 MM, DIE-166
文件頁數(shù): 26/48頁
文件大小: 427K
代理商: S-4561A
LCD Controller-Driver
S-4561A
32
Seiko Instruments Inc.
4.
Procedures from Powering ON to Display Start
The procedures from powering ON to Display Start are as follows:
Mode Setting Examples after Powering ON
5.
Instruction Execution Time
Any instructions other than the DISPLAY CLEAR are completed within the cycle time (tcyc) represented with the instruction
input timing characteristics. For instance, when the instruction input cycle time is 500
sec, the instruction can be completed
within 500
sec. Consequently, instructions can be input in succession without confirming the BUSY flag. Also, load to the
MPU and the current consumption can be drastically reduced. Inputting the next command within the cycle time is
prohibited.
In the DISPLAY CLEAR mode, it is necessary to write a space code in all of DDRAMs. For the write execution time, refer to
page 18, “Instruction Explanation” of this specification.
6.
Read and Write Display Data from and In MPU
The Display Data is accessed from the MPU to DDRAM, CGRAM, ICONRAM or ICON BLINK RAM by executing the READ
or WRITE command following the ADDRESS SETTING command of individual RAMs. Always execute the ADDRESS
SETTING command before executing the READ command. When the ADDRESS SETTING command is not executed,
correct display data cannot be read. After executing the READ or WRITE command, the column address is incremented or
decremented depending upon the value of the ID of the ENTRY MODE Setting. Consequently, when the cycle time
represented
q
DL=1
8-bit data length
interface
q
N=0
2-line x 12-column
q
MS=0
Normal Instruction
q
DT=0
5-dot font
0
Setting Examples:
RS
0
R/WX
0
DB7
0
DB6
1
DB5
1
DB4
0
DB3
0
DB2
0
DB1
-
DB0
0
1
0
1
0
1
0
-
q
DL=1
8-bit data length
interface
q
N=0
2-line x 12-column
q
MS=1
Extended Instruction
q
DT=0
5-dot font
Normal Function Setting
0
1
0
Powering ON
RESX Input
Wait Time
Initialize.
Wait for BUSY cancellation.
When you do not want monitor BUSY*, wait for 2.0 msec at fosc=34 kHz.
Extended Function Setting
q
ID=0
Decrement
q
S=0
No Display Shift
Display ON/OFF
q
D=1
Display ON
q
C=1
Cursor Display ON
q
B=0
Cursor Blink OFF
Entry Mode Setting
Power Save Release
0
q
PS=0
Power Save Cancel
*
Set the wait time twice as long as fosc35 clock.
When BUSY is canceled, this IC is set to the power save mode (PS=1) .
Bias Select
0
1
0
1
0
-
1
q
MLC=0 No COM output inversion
q
MLS=0 No SEG output inversion
q
BS5=1 1/5 bias
Write in the specified instruction set, CGRAM, DDRAM, and ICONRAM.
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