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參數(shù)資料
| 型號(hào)： | RTL8309SB |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER |
| 中文描述： | 單芯片9口10/100Mbps開關(guān)控制器 |
| 文件頁數(shù)： | 96/115頁 |
| 文件大?。?/td> | 866K |
| 代理商： | RTL8309SB |
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RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller
81
Track ID: JATR-1076-21 Rev. 1.4
8.3.8.
Lookup Table Access
The RTL8309SB supports registers for the CPU to read/write to an internal 1024-entry lookup table via the SMI interface.
Before reading/writing from/to the internal forwarding table, the contents of internal register ‘Indirect Access Control [15:0]’
should be filled correctly.
In a write cycle, the user must assign the write data in register
‘
Indirect Access Data [63:0]’ first. Bits 1~0 along with bits 15~8
form a 10-bit field that indirectly maps to an entry in the lookup table. To execute a write access, bit 0 in the ‘Indirect Access
Control’ register should be set to 0, and bit 1 should be set to 1. The CPU will poll bit 1 in ‘Indirect Access Control’ to
determine whether the write access is complete or not.
The 10-bit field composed of bits 1~0 and bits 15~8 in PHY7 Reg.20 indirectly maps to an entry in the lookup table for
reading. The read back data is shown in PHY7 Reg.17~20. To execute read access, bit 0 in the ‘Indirect Access Control’
register should be set to 1, and bit 1 should be set to 1 to trigger this command. The CPU will poll bit 1 in ‘Indirect Access
Control’ to determine whether read access is complete or not.
8.3.9.
Serial Management Interface (SMI)
SMI is also known as the MII Management Interface. It consists of two signals (MDIO and MDC) that allow an external
device in SMI master mode (MDC is output) to control the state of PHY, and in SMI slave mode (MDC is input) to control the
internal register. MDC is an input clock for the RTL8309SB to latch MDIO on its rising edge. The clock can run from 0MHz
to 25MHz. MDIO is a bi-directional signal that is used to write data to, or read data from, the RTL8309SB. Table 111 shows
the read and write cycle format of the RTL8309SB.
Table 111. SMI Read/Write Cycles
OP Code
(2 bits)
(5 bits)
10
A
4
A
3
A
2
A
1
A
0
01
A
4
A
3
A
2
A
1
A
0
Preamble
(32 bits)
1……..1
1……..1
Start
(2 bits)
01
01
PHYAD
REGAD
(5 bits)
R
4
R
3
R
2
R
1
R
0
R
4
R
3
R
2
R
1
R
0
Turn Around
(2 bits)
Z0
10
Data
(16 bits)
D
15
…….D
0
D
15
…….D
0
Idle
Z*
Z*
Read
Write
*Z: high-impedance. During idle time, an external 1.5K
pull-up resistor determines MDIO state.
The RTL8309B supports Preamble Suppression, which allows the MAC to issue Read/Write Cycles without preamble bits.
However, for the first cycle of MII management after power-on reset, a 32-bit preamble is needed.
To guarantee the first successful SMI transaction after power-on reset, an external device should delay at least 1 second before
issuing the first SMI Read/Write Cycle relative to the rising edge of reset. The output voltage level of the RTL8309SB is
configurable by supplying different voltages to pin VDDIO. VDDIO can be supplied with either 2.5V or 3.3V power.
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| RU4D | SDR Cable Assembly; Connector Type A:micro D Ribbon Plug; Connector Type B:micro D Ribbon Plug; Cable Length:2m; No. of Contacts:26; Pitch Spacing:0.8mm RoHS Compliant: Yes |
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