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參數(shù)資料
| 型號(hào)： | RTL8309SB |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER |
| 中文描述： | 單芯片9口10/100Mbps開(kāi)關(guān)控制器 |
| 文件頁(yè)數(shù)： | 111/115頁(yè) |
| 文件大?。?/td> | 866K |
| 代理商： | RTL8309SB |
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RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller
96
Track ID: JATR-1076-21 Rev. 1.4
11. Design and Layout Guide
In order to achieve maximum performance using the RTL8309SB, good design attention is required throughout the design and
layout process. The following are some recommendations on how to implement a high performance system.
General Guidelines
Provide a good power source, minimizing noise from switching power supply circuits (<50mV).
Keep power and ground noise levels below 50mV.
Verify the ability of critical components, e.g., clock source and transformer, to meet application requirements.
Use bulk capacitors (4.7
μ
F-10
μ
F) between the power and ground planes.
Use 0.1
μ
F de-coupling capacitors to reduce high-frequency noise on the power and ground planes.
Keep de-coupling capacitors as close as possible to the RTL8309SB.
Differential Signal Layout Guidelines
Keep differential pairs as close as possible and route both traces as identically as possible.
Avoid vias and layer changes if possible.
Keep transmit and receive pairs away from each other. Run orthogonal or separate by a ground plane.
Keep each different pair on the same plane.
Clock Circuit
The clock should be 25M 100ppm with jitter less than 0.5ns.
If possible, surround the clock by ground trace to minimize high-frequency emissions.
Power Planes
Divide the power plane into 1.8V digital, 1.8V analog.
Use 0.1
μ
F decoupling capacitors and bulk capacitors between each power plane and ground plane.
Place two 47
μ
F bulk capacitors on the device-side (primary) center tap of the transformer.
Ground Plane
Keep the system ground region as one continuous, unbroken plane that extends from the primary side of the transformer
to the rest of the board.
Place a moat (gap) between the system ground and chassis ground.
Ensure the chassis ground area is voided at some point such that no ground loop exists on the chassis ground area.
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