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參數(shù)資料
| 型號(hào)： | RTL8309SB |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER |
| 中文描述： | 單芯片9口10/100Mbps開(kāi)關(guān)控制器 |
| 文件頁(yè)數(shù)： | 13/115頁(yè) |
| 文件大小： | 866K |
| 代理商： | RTL8309SB |
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RTL8309SB
Datasheet
Single-Chip 9-Port 10/100Mbps Switch Controller
xiii
Track ID: JATR-1076-21 Rev. 1.4
Table 69. PHY 0 Register 6: Auto-Negotiation Expansion.........................................................................43
Table 70. PHY 0 Register 16: Global Control 0..........................................................................................43
Table 71. PHY 0 Register 17: Global Control 1..........................................................................................45
Table 72. PHY 0 Register 18: Global Control 2..........................................................................................46
Table 73. PHY 0 Register 19: Global Control 3..........................................................................................46
Table 74. PHY 0 Register 22: Port 0 Control 0...........................................................................................46
Table 75. PHY 0 Register 23: Port 0 Control 1...........................................................................................48
Table 76. PHY 0 Register 24: Port 0 Control 2 & VLAN Entry [A]...........................................................48
Table 77. PHY 0 Register 25: VLAN Entry [A]..........................................................................................48
Table 78. PHY 1 Register 16~17: IP Priority Address [A]..........................................................................49
Table 79. PHY 1 Register 18~19: IP Priority Address [B]..........................................................................49
Table 80. PHY 1 Register 24: Port 1 Control 2 & VLAN Entry [B]...........................................................50
Table 81. PHY 1 Register 25: VLAN Entry [B]..........................................................................................50
Table 82. PHY 2 Register 16~17: IP Priority Mask [A]..............................................................................51
Table 83. PHY 2 Register 18~19: IP Priority Mask [B]..............................................................................51
Table 84. PHY 2 Register 24: Port 2 Control 2 & VLAN Entry [C]...........................................................52
Table 85. PHY 2 Register 25: VLAN Entry [C]..........................................................................................52
Table 86. PHY 3 Register 16~18: Switch MAC Address............................................................................53
Table 87. PHY 3 Register 24: Port 3 Control 2 & VLAN Entry [D]...........................................................53
Table 88. PHY 3 Register 25: VLAN Entry [D]..........................................................................................53
Table 89. PHY 4 Register 16~18: ISP MAC Address .................................................................................54
Table 90. PHY 4 Register 24: Port 4 Control 2 & VLAN Entry [E]...........................................................55
Table 91. PHY 4 Register 25: VLAN Entry [E]..........................................................................................55
Table 92. PHY 5 Register 16: MII Port Control 0.......................................................................................56
Table 93. PHY 5 Register 17: MII Port Control 1 & VLAN Entry [I]........................................................57
Table 94. PHY 5 Register 18: VLAN Entry [I]...........................................................................................57
Table 95. PHY 5 Register 19: CPU Port & WAN Port................................................................................57
Table 96. PHY 5 Register 24: Port 5 Control 2 & VLAN Entry [F] ...........................................................58
Table 97. PHY 5 Register 25: VLAN Entry [F] ..........................................................................................58
Table 98. PHY 6 Register 24: Port 6 Control 2 & VLAN Entry [G]...........................................................60
Table 99. PHY 6 Register 25: VLAN Entry [G]..........................................................................................60
Table 100. PHY 7 Register 16: Indirect Access Control .............................................................................61
Table 101. PHY 7 Register 17~20: Indirect Access Data............................................................................62
Table 102. PHY 7 Register 24: Port 7 Control 2 & VLAN Entry [H].........................................................62
Table 103. PHY 7 Register 25: VLAN Entry [H]........................................................................................63
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