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參數(shù)資料
| 型號： | RTL8309SB |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER |
| 中文描述： | 單芯片9口10/100Mbps開關(guān)控制器 |
| 文件頁數(shù)： | 80/115頁 |
| 文件大?。?/td> | 866K |
| 代理商： | RTL8309SB |
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RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller
65
Track ID: JATR-1076-21 Rev. 1.4
7.9.4.
MII Port NWay Mode
Table 107. MII Port NWay Mode
Condition
Upon Reset
Description
Strapping MII_SPD_STA=1 and MII_DUP_STA=1
Strapping MII_SPD_STA=1 and MII_DUP_STA=0
Strapping MII_SPD_STA=0 and MII_DUP_STA=1
Strapping MII_SPD_STA=0 and MII_DUP_STA=0
Defau1t value of Reg4.10 is strapped from pin MII_FCTRL_STA
Default value of Reg1.2 is strapped from pin MII_LNK_STA#.
MII_LNK_STA# pulled down
Reg1.2=1.
MII_LNK_STA# pulled up
Reg1.2=0.
If PHY 8 register 4 is configured as Reg4.8=1, Reg4.7=1, Reg4.6=1, Reg4.5=1, the RTL8309SB
will reflect this configuration in PHY 8 register 0 as Reg0.13=1 and Reg0.8=1.
If PHY 8 register 4 is configured as Reg4.8=0, Reg4.7=1, Reg4.6=1, Reg4.5=1, the RTL8309SB
will reflect this configuration in PHY 8 register 0 as Reg0.13=1 and Reg0.8=0.
If PHY 8 register 4 is configured as Reg4.8=0, Reg4.7=0, Reg4.6=1, Reg4.5=1, the RTL8309SB
will reflect this configuration in PHY 8 register 0 as Reg0.13=0 and Reg0.8=1.
If PHY 8 register 4 is configured as Reg4.8=0, Reg4.7=0, Reg4.6=0, Reg4.5=1, the RTL8309SB
will reflect this configuration in PHY 8 register 0 as Reg0.13=0 and Reg0.8=0.
If the CPU polls register 5, the RTL8309SB replies with the contents in register 4.
If the CPU polls register 4, the RTL8309SB replies with the contents in register 4.
Reg0.13=1, Reg0.8=1
Reg0.13=1, Reg0.8=0
Reg0.13=0, Reg0.8=1
Reg0.13=0, Reg0.8=0
After Reset
7.9.5.
MII Port Force Mode
Table 108. MII Port Force Mode
Condition
Upon Reset
Description
Strapping MII_SPD_STA=1 and MII_DUP_STA=1
Strapping MII_SPD_STA=1 and MII_DUP_STA=0
Strapping MII_SPD_STA=0 and MII_DUP_STA=1
Strapping MII_SPD_STA=0 and MII_DUP_STA=0
Defau1t value of Reg4.10 is strapped from pin MII_FCTRL_STA.
Default value of Reg1.2 is strapped from pin MII_LNK_STA#.
MII_LNK_STA# pulled down
Reg1.2=1.
MII_LNK_STA# pulled up
Reg1.2=0.
The CPU only writes register 0.13 and 0.8 to configure a link status, then reads register 1.2 to
determine whether the link partner can link with this status.
Reg0.13=1, Reg0.8=1
Reg0.13=1, Reg0.8=0
Reg0.13=0, Reg0.8=1
Reg0.13=0, Reg0.8=0
After Reset
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