參數(shù)資料
型號(hào): RTL8309SB
廠商: Electronic Theatre Controls, Inc.
英文描述: SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER
中文描述: 單芯片9口10/100Mbps開關(guān)控制器
文件頁數(shù): 65/115頁
文件大小: 866K
代理商: RTL8309SB
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller
50
Track ID: JATR-1076-21 Rev. 1.4
7.2.8.
PHY 1 Register 22: Port 1 Control 0
This register has the same definition as PHY 0 Register 22: Port 0 Control 0, page 46.
Note: Reg 22.8 is not pin Sel_PortPri strap option for port 1. Default value for 22.8 is 1.
7.2.9.
PHY 1 Register 23: Port 1 Control 1
This register has the same definition as PHY 0 Register 23: Port 0 Control 1, page 48.
7.2.10. PHY 1 Register 24: Port 1 Control 2 & VLAN Entry [B]
Table 80. PHY 1 Register 24: Port 1 Control 2 & VLAN Entry [B]
Mode Description
24[15~12] Port 1 VLAN index
[3:0]
1’s ‘Port VLAN Membership’, which could be defined in one of
the registers ‘VLAN ID [A] Membership’ to ‘VLAN ID [I]
Membership’. Port 1 can only communicate within the
membership. This register also indexes to a default Port VID
(PVID) for each port. The PVID is used in tag insertion and
filtering if the tagged VID is not the same as the PVID.
24.[11:9] Reserved
24.[8:0] VLAN ID [B]
Membership Bit
[8:0]
this VLAN will be forwarded to ports specified in this field.
E.g., 1 0000 0001 means port 8 and 0 are in this VLAN.
Reg.bit
Name
Default
0001
RW
In a port-based VLAN configuration, this register indexes port
111
1
0000
0010
RW
This 9-bit field specifies which ports are members of VLAN B.
If a destination address look up fails, packets associated with
7.2.11. PHY 1 Register 25: VLAN Entry [B]
Table 81. PHY 1 Register 25: VLAN Entry [B]
Mode Description
RW
Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN B.
Reg.bit
25.[15:12] Reserved
25[11:0] VLAN ID [B]
Name
Default
1111
0000
0000
0001
7.3.
PHY 2 Registers
7.3.1.
PHY 2 Register 0: Control
This register has the same definition as PHY 0 Register 0: Control, page 40.
7.3.2.
PHY 2 Register 1: Status
This register has the same definition as PHY 0 Register 1: Status, page 41.
7.3.3.
PHY 2 Register 4: Auto-Negotiation Advertisement
This register has the same definition as PHY 0 Register 4: Auto-Negotiation Advertisement, page 42.
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