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參數(shù)資料
| 型號： | RTL8309SB |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER |
| 中文描述： | 單芯片9口10/100Mbps開關(guān)控制器 |
| 文件頁數(shù)： | 78/115頁 |
| 文件大?。?/td> | 866K |
| 代理商： | RTL8309SB |
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RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller
63
Track ID: JATR-1076-21 Rev. 1.4
Reg.bit
24.[8:0] VLAN ID [H]
Membership Bit
[8:0]
Name
Mode Description
RW
This 9-bit field specifies which ports are members of VLAN H.
If a destination address look up fails, packets associated with
this VLAN will be forwarded to ports specified in this field.
E.g., 1 0000 0001 means port 8 and 0 are in this VLAN.
Default
1
1000
0000
7.8.11. PHY 7 Register 25: VLAN Entry [H]
Table 103. PHY 7 Register 25: VLAN Entry [H]
Mode Description
RW
Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN H.
Reg.bit
25.[15:12] Reserved
25.[11:0] VLAN ID [H]
Name
Default
1111
0000
0000
0111
7.9.
PHY 8 Registers
7.9.1.
PHY 8 Register 0: Control
Note: This register only works in MII PHY and SNI PHY mode. In MII MAC mode, these registers have no meaning.
Table 104. PHY 8 Register 0: Control
Mode Description
RO
0: No reset allowed (permanently=0)
RO
0: Normal operation (permanently=0)
Reg.bit
0.15
0.14
Name
Reset
Loopback
(digital loopback)
Speed Select
Default
0
0
0.13
RW
1: 100Mbps
0: 10Mbps
When NWay is enabled, this bit reflects the result of auto-
negotiation (Read only).
When NWay is disabled, this bit can be set through SMI
(Read/Write).
1: Enable auto-negotiation process
0: disable auto-negotiation process
This bit can be set through SMI (Read/Write).
0: Normal operation (permanently=0)
0: Normal operation (permanently=0)
0: Normal operation (permanently=0)
Pin MII_SPD
_STA strap
option
0.12
Auto Negotiation
Enable
RW
1
0.11
0.10
0.9
Power Down
Isolate
Restart Auto
Negotiation
Duplex Mode
RO
RO
RO
0
0
0
0.8
RW
1: Full duplex operation
0: Half duplex operation
When NWay is enabled, this bit reflects the result of auto-
negotiation (Read only).
When NWay is disabled, this bit may be set through SMI
(Read/Write).
Pin MII_DUP
_STA strap
option
0.[7:0]
Reserved
0
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