參數(shù)資料
型號(hào)： RTL8309SB
廠商： Electronic Theatre Controls, Inc.
英文描述： SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER
中文描述： 單芯片9口10/100Mbps開關(guān)控制器
文件頁數(shù)： 27/115頁
文件大小： 866K
代理商： RTL8309SB
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller
12
Track ID: JATR-1076-21 Rev. 1.4
Pin Name
SDA_MDIO
Pin No.
55
Type Description
I/O
EEPROM Serial Data Input/Output or MDIO.
This pin is three state when pin RESET#=0.
When the RTL8309SB detects an EEPROM connected to it, this pin
becomes SDA (input/output) to load the serial EEPROM upon reset.
The pin changes to MDIO (input/output) after reset.
When the RTL8309SB does not detect an EEPROM connected to it,
this pin is MDIO (input/output). It should be pulled high by an
external resistor.
Default
-
5.6.
Strapping Pins
Note: All strapping pins are dual function pins: output for LED and input for strapping. The table below covers strapping only.
See Port LED Pins, on page 9, for LED pin settings.
Table 7. Strapping Pins
Type Description
I
pu
Input upon reset = Enable Auto-negotiation function.
1: Enable the auto-negotiation function (NWay mode) and set PHY
register 0.12
0: Disable the auto-negotiation function (force mode) and deselect
PHY register 0.12
Output after reset = used for LED.
I
pu
Input upon reset = Enable flow control ability in full duplex mode.
1: In NWay mode, this pin sets PHY register 4.10, but the flow
control function is finally enabled based on the auto negotiation
result. In force mode, this pin will always enable the flow control
function
0: Disable the flow control function
Output after reset = used for LED.
I
pu
Input upon reset = Enable backpressure ability in half duplex mode.
1: Enable backpressure
0: Disable backpressure
Output after reset = used for LED.
I
pu
Force duplex mode.
This pin sets PHY Reg.0.8 and influences the contents of PHY
Reg.4.
1: Force full duplex if auto-negotiation is disabled
0: Force half duplex if auto-negotiation is disabled
Output after reset = used for LED.
I
pu
Force operating speed.
This pin sets PHY Reg.0.13 and influences the contents of PHY
Reg.4.
1: Force 100Mbps speed if auto-negotiation is disabled
0: Force 10Mbps speed if auto-negotiation is disabled
Output after reset = used for LED.
Pin Name
En_ANEG
/P1_LED[2]
Pin No.
104
Default
1
En_FCTRL
/P1_LED[1]
105
1
En_BKPRS
/P1_LED[0]
106
1
Force_Duplex
/P0_LED[3]
109
1
Force_Speed
/P0_LED[2]
110
1
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