參數(shù)資料
型號: R1Q2A3609BBG-50RB
元件分類: SRAM
英文描述: 4M X 9 QDR SRAM, PBGA165
封裝: 15 X 17 MM, 1 MM PITCH, LEAD FREE, PLASTIC, LBGA-165
文件頁數(shù): 9/26頁
文件大小: 341K
代理商: R1Q2A3609BBG-50RB
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 17 of 24
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with normal
operation of the device, TCK must be tied to V
SS
to preclude mid level inputs. TDI and TMS are designed so an
undriven input will produce a response identical to the application of a logic 1,and may be left unconnected. But they
may also be tied to VDD through a 1k
resistor.TDO should be left unconnected.
Test Access Port (TAP) Pins
Symbol I/O
Pin assignments
Description
Notes
TCK
2R
Test clock input. All inputs are captured on the rising edge of TCK and all
outputs propagate from the falling edge of TCK.
TMS
10R
Test mode select. This is the command input for the TAP controller state
machine.
TDI
11R
Test data input. This is the input side of the serial registers placed between
TDI and TDO. The register placed between TDI and TDO is determined by
the state of the TAP controller state machine and the instruction that is
currently loaded in the TAP instruction.
TDO
1R
Test data output. Output changes in response to the falling edge of TCK.
This is the output side of the serial registers placed between TDI and TDO.
Notes: The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for
five rising edges of TCK. The TAP controller state is also reset on SRAM POWER-UP.
TAP DC Operating Characteristics
(Ta = 0 to +70
°C, VDD = 1.8V ± 0.1V)
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Input high voltage
VIH
+1.3
VDD + 0.3
V
Input low voltage
VIL
0.3
+0.5
V
Input leakage current
ILI
5.0
+5.0
A
0 V
≤ VIN ≤ VDD
Output leakage current
ILO
5.0
+5.0
A
0 V
≤ VIN ≤ VDD,
output disabled
Output low voltage
VOL1
0.2
V
IOLC = 100
A
VOL2
0.4
V
IOLT = 2 mA
Output high voltage
VOH1
1.6
V
|IOHC| = 100
A
VOH2
1.4
V
|IOHT| = 2 mA
Notes: 1. All voltages referenced to VSS (GND).
2. Power-up: VIH
≤ VDDQ + 0.3 V and VDD ≤ +1.7 V and VDDQ ≤ +1.4 V for t ≤ 200 ms.
3. In “EXTEST” mode and “SAMPLE” mode, VDDQ is nominally 1.5 V.
4. ZQ: VIH = VDDQ.
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