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參數(shù)資料
| 型號： | R1Q2A3609BBG-50RB |
| 元件分類： | SRAM |
| 英文描述： | 4M X 9 QDR SRAM, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, LEAD FREE, PLASTIC, LBGA-165 |
| 文件頁數(shù)： | 26/26頁 |
| 文件大?。?/td> | 341K |
| 代理商： | R1Q2A3609BBG-50RB |
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R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 9 of 24
K Truth Table
Operation
K
/R
/W
D or Q
Data in
Input data
D(A+0)
D(A+1)
Write Cycle:
Load address, input write data on
consecutive K and /K rising edges
↑
×
L
Output clock
K(t)
↑
/K(t)
↑
Data out
Output data
Q(A+0)
Q(A+1)
Read Cycle:
Load address, output read data on
consecutive C and /C rising edges
↑
L
×
Output clock
/C(t+1)
↑
C(t+2)
↑
NOP (No operation)
↑
H
D =
× or Q = High-Z
Standby (Clock stopped)
Stopped
×
Previous state
Notes: 1. H: high level, L: low level,
×: don’t care, ↑: rising edge.
2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges,
except if C and /C are high, then data outputs are delivered at K and /K rising edges.
3. /R and /W must meet setup/hold times around the rising edges (low to high) of K and are registered at the
rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. When clocks are stopped, the following cases are recommended; the case of K = low, /K = high, C = low and
/C = high, or the case of K = high, /K = low, C = high and /C = low. This condition is not essential, but permits
most rapid restart by overcoming transmission line charging symmetrically.
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| R1Q2A3609BBG-60R | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
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| R1Q2A3609RBG-40RS0 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
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