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參數(shù)資料
| 型號： | R1Q2A3609BBG-50RB |
| 元件分類： | SRAM |
| 英文描述： | 4M X 9 QDR SRAM, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, LEAD FREE, PLASTIC, LBGA-165 |
| 文件頁數(shù)： | 24/26頁 |
| 文件大?。?/td> | 341K |
| 代理商： | R1Q2A3609BBG-50RB |
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R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 7 of 24
General Description
Power-up and Initialization Sequence
The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN.
After the stable power, there are three possible sequences.
1. Sequence when DLL disable (/DOFF pin fixed low)
Just after the stable power and clock (K, /K, C, /C), 1024 NOP cycles (min.) are required for all operations,
including JTAG functions, to become normal.
2a. Sequence controlled by /DOFF pin when DLL enable
Just after the stable power and clock (K, /K, C, /C), take /DOFF to be high.
The additional 1024 NOP cycles (min.) are required to lock the DLL and for all operations to become normal.
2b. Sequence controlled by Clock (/DOFF pin fixed high) when DLL enable
If /DOFF pin is fixed high with unstable clock, the clock (K, /K, C, /C) must be stopped for 30ns (min.).
During stop clock stage, C pin must tie low for 30 ns (min.). C, /C, K and /K cannot remain VREF level.
The additional 1024 NOP cycles (min.) are required to lock the DLL and for all operations to become normal.
Notes: 1. After K or C clock is stopped, clock recovery cycles (1024 NOP cycles (min.)) are required for read/write
operations to become normal.
2. When DLL is enable and the operating frequency is changed, DLL reset should be required again. After DLL
reset again, the 1024 NOP cycles (min.) are needed to lock the DLL.
1. Sequence when DLL disable (/DOFF pin fixed low)
Status
Power Up
Unstable
Clock Stage
Stable
Clock Stage
NOP Stage
Normal
Operation
VDD
C, /C, K, /K
VDDQ
VREF
VIN
1024cycle min.
2a. Sequence controlled by /DOFF pin when DLL enable
Status
Power Up
Unstable
Clock Stage
Stable
Clock Stage
NOP & DLL
Locking Stage
Normal
Operation
VDD
C, /C, K, /K
1024cycle min.
VDDQ
/DOFF
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|---|---|
| R1Q2A3609BBG-60R | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q2A3609RBG-40RB0 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q2A3609RBG-40RS0 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q2A3609RBG-40RT0 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q2A3609RBG-50RB0 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
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